)]}'
{
  "commit": "0fb95e54c6ac2270bff620285c73a6f9e95a61e3",
  "tree": "70111718d73851950fe0bcf05c0f27d7c1e77030",
  "parents": [
    "f05a56d2cec2ac9304aaeb613b0d44d3d0187c32",
    "3aa88ede1cab4d4dfde79bd0f285a043d1249bf5"
  ],
  "author": {
    "name": "Alessandro Comodi",
    "email": "44773360+acomodi@users.noreply.github.com",
    "time": "Mon Nov 30 12:17:57 2020 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon Nov 30 12:17:57 2020 +0100"
  },
  "message": "Merge pull request #57 from antmicro/sdc_skip_clocks_on_dangling_wires\n\nSDC: Skip adding clocks on dangling wires",
  "tree_diff": []
}