tree 70111718d73851950fe0bcf05c0f27d7c1e77030
parent f05a56d2cec2ac9304aaeb613b0d44d3d0187c32
parent 3aa88ede1cab4d4dfde79bd0f285a043d1249bf5
author Alessandro Comodi <44773360+acomodi@users.noreply.github.com> 1606735077 +0100
committer GitHub <noreply@github.com> 1606735077 +0100
gpgsig -----BEGIN PGP SIGNATURE-----
 
 wsBcBAABCAAQBQJfxNTlCRBK7hj4Ov3rIwAAdHIIADy5tihiBigThQThe8H2KB4f
 18tGOmaog0dglHWq2visK74j+8j7ZrGLJutW4CImTcQThgBzqCMyM075QnIwrQ/E
 c+hoaWd1siTuhBZoTZazWa3WRJLhEP53m+ae6nQcrTETY1KGGpPQcR3oD6+sPxHR
 Z7ZXwfa0mHlhXf2nXYi7XDZqTTUy9YS5neAHTbFO8rh7AB+Tx1jCpW8J3McTPF+W
 H6eNlZSalrkfbuMX9EIUrhAAHIUrvc4A5OiZTSXKk+M7XdlErggP8kVoABWrJ7R3
 a5GzgsrRhYNjiBlfsTmrlckNUpWISsJ06Fjmbznebnp/5YRGxg4jjqLvkM8Slos=
 =j60x
 -----END PGP SIGNATURE-----
 

Merge pull request #57 from antmicro/sdc_skip_clocks_on_dangling_wires

SDC: Skip adding clocks on dangling wires