)]}'
{
  "commit": "0fba5f0fc5b000b9cfbea220315d7ef74b7e775b",
  "tree": "477eeb95395549601447ec95362ebf48af36b6b5",
  "parents": [
    "9852a6ae2e0b0f2297d6ed407b2d9da494e56491"
  ],
  "author": {
    "name": "Rafal Kapuscik",
    "email": "rkapuscik@antmicro.com",
    "time": "Tue Mar 15 14:59:57 2022 +0100"
  },
  "committer": {
    "name": "Rafal Kapuscik",
    "email": "rkapuscik@antmicro.com",
    "time": "Wed Mar 23 14:09:47 2022 +0100"
  },
  "message": "Traverse both allPackages and topPackages\n\nSigned-off-by: Rafal Kapuscik \u003crkapuscik@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "285f0bd84ad4df9db96f1a6a327da6fd6cd5b0b5",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "a94767ac2faa23a06f53305c89f3d3c44a270d39",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}