)]}'
{
  "commit": "1009fa45d59900b9e837a9e852289afc06aef388",
  "tree": "09d5e967e47db6fbe4572a18add8ba4ef030f21f",
  "parents": [
    "6689e20e5fdb0b8d6f494acd65b08fd4646edc0e"
  ],
  "author": {
    "name": "Wojciech Sipak",
    "email": "wsipak@antmicro.com",
    "time": "Mon Jun 05 13:46:53 2023 +0200"
  },
  "committer": {
    "name": "Wojciech Sipak",
    "email": "wsipak@antmicro.com",
    "time": "Wed Jun 07 13:30:08 2023 +0200"
  },
  "message": "process hier paths\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ffa766ecc3c6a3c8dfc7779d64db11f0d7a0cae9",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "59c95d7b17fd84db93b76ddcbc758ea903894a20",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}