)]}'
{
  "commit": "1256b0a4297dfa53371f8f63c1c8efa80fb146d5",
  "tree": "89ce7c6c6091bad59d6357d356dd3b5196389ac3",
  "parents": [
    "64ace4518bb4d36b64feb8d48195255b092be5c2",
    "dcfdb903e1284c24a87f9a6010c2e1e7f0c25289"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Thu Apr 07 11:31:21 2022 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Apr 07 11:31:21 2022 +0200"
  },
  "message": "Merge pull request #294 from antmicro/fix-visit-debug\n\nSystemVerilog: fix read_uhdm frontend",
  "tree_diff": []
}