commit 137606ebfad8de60aa44d37c11a20c540bbdba98
author Kamil Rakoczy <krakoczy@antmicro.com> Thu Apr 20 12:04:45 2023 +0200
committer GitHub <noreply@github.com> Thu Apr 20 12:04:45 2023 +0200
tree 86e50cc28afdd60f330b94014e61cc00dcd19f1b
parent 3a440c4d33e47849e4d974f0bd65bb40272716e9
parent f9168973b04e6a4eb59402f0bfb880c3c771850c

Merge pull request #487 from antmicro/kr/fix_genscope_param

systemverilog-plugin: replace default parameter definition in genscope

systemverilog-plugin/UhdmAst.cc

diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index 37b7d79..a9ee630 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -4004,7 +4004,10 @@
         lhs_node = new AST::AstNode(AST::AST_IDENTIFIER);
         auto ancestor = find_ancestor({AST::AST_WIRE, AST::AST_MEMORY, AST::AST_PARAMETER, AST::AST_LOCALPARAM});
         if (!ancestor) {
-            log_error("Couldn't find ancestor for tagged pattern!\n");
+            const uhdm_handle *const handle = (const uhdm_handle *)obj_h;
+            const UHDM::BaseClass *const object = (const UHDM::BaseClass *)handle->object;
+            report_error("%.*s:%d: Couldn't find ancestor for tagged pattern!\n", (int)object->VpiFile().length(), object->VpiFile().data(),
+                         object->VpiLineNo());
         }
         lhs_node->str = ancestor->str;
     }