commit 14d36704fcd4787d9767fc0359cc7be075559d9b
author Mariusz Glebocki <mglebocki@antmicro.com> Mon Mar 27 20:51:13 2023 +0200
committer Mariusz Glebocki <mglebocki@antmicro.com> Mon Mar 27 20:51:13 2023 +0200
tree 59c58669959292122b046577df910d455c825bae
parent 23669fb15ae896ba0493ef4387f8551f5b034fdd

Initialize and cleanup attr_ids before/after design processing.

systemverilog-plugin/UhdmAst.cc

diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index 0025a17..40e80cd 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -53,6 +53,7 @@
 static IdString low_high_bound;
 }; // namespace attr_id
 
+// TODO(mglb): use attr_id::* directly everywhere and remove those methods.
 /*static*/ const IdString &UhdmAst::partial() { return attr_id::partial; }
 /*static*/ const IdString &UhdmAst::packed_ranges() { return attr_id::packed_ranges; }
 /*static*/ const IdString &UhdmAst::unpacked_ranges() { return attr_id::unpacked_ranges; }
@@ -61,7 +62,7 @@
 /*static*/ const IdString &UhdmAst::is_simplified_wire() { return attr_id::is_simplified_wire; }
 /*static*/ const IdString &UhdmAst::low_high_bound() { return attr_id::low_high_bound; }
 
-void UhdmAst::static_init()
+void attr_id_init()
 {
     // Initialize only once
     static bool already_initialized = false;
@@ -82,6 +83,18 @@
     attr_id::low_high_bound = IdString("$systemverilog_plugin$low_high_bound");
 }
 
+void attr_id_cleanup()
+{
+    // Release static copies of private IdStrings.
+    attr_id::low_high_bound = IdString();
+    attr_id::is_simplified_wire = IdString();
+    attr_id::is_imported = IdString();
+    attr_id::force_convert = IdString();
+    attr_id::unpacked_ranges = IdString();
+    attr_id::packed_ranges = IdString();
+    attr_id::partial = IdString();
+}
+
 static void sanitize_symbol_name(std::string &name)
 {
     if (!name.empty()) {
@@ -4715,6 +4728,8 @@
 
 AST::AstNode *UhdmAst::visit_designs(const std::vector<vpiHandle> &designs)
 {
+    attr_id_init();
+
     current_node = new AST::AstNode(AST::AST_DESIGN);
     for (auto design : designs) {
         UhdmAst ast(this, shared, indent);
@@ -4725,14 +4740,7 @@
         }
     }
 
-    // Release static copies of private IdStrings. Those should be last instances in use.
-    attr_id::low_high_bound = IdString();
-    attr_id::is_simplified_wire = IdString();
-    attr_id::is_imported = IdString();
-    attr_id::force_convert = IdString();
-    attr_id::unpacked_ranges = IdString();
-    attr_id::packed_ranges = IdString();
-    attr_id::partial = IdString();
+    attr_id_cleanup();
 
     return current_node;
 }

systemverilog-plugin/UhdmAst.h

diff --git a/systemverilog-plugin/UhdmAst.h b/systemverilog-plugin/UhdmAst.h
index ad71834..81679e3 100644
--- a/systemverilog-plugin/UhdmAst.h
+++ b/systemverilog-plugin/UhdmAst.h
@@ -168,11 +168,6 @@
     // Visits all VPI design objects and returns created ASTs
     ::Yosys::AST::AstNode *visit_designs(const std::vector<vpiHandle> &designs);
 
-    // Does initialization of the class global data.
-    // Must be called before the first use of the class.
-    // Can be called multiple times; only the first call performs actual initialization.
-    static void static_init();
-
     static const ::Yosys::IdString &partial();
     static const ::Yosys::IdString &packed_ranges();
     static const ::Yosys::IdString &unpacked_ranges();

systemverilog-plugin/uhdmsurelogastfrontend.cc

diff --git a/systemverilog-plugin/uhdmsurelogastfrontend.cc b/systemverilog-plugin/uhdmsurelogastfrontend.cc
index 4233357..a0e71a6 100644
--- a/systemverilog-plugin/uhdmsurelogastfrontend.cc
+++ b/systemverilog-plugin/uhdmsurelogastfrontend.cc
@@ -130,8 +130,6 @@
         this->print_read_options();
     }
 
-    virtual void on_register() override { UhdmAst::static_init(); }
-
     AST::AstNode *parse(std::string filename) override
     {
         std::vector<const char *> cstrings;