diff --git a/sdc-plugin/tests/counter/counter.sdc b/sdc-plugin/tests/counter/counter.sdc
index 796e849..01debad 100644
--- a/sdc-plugin/tests/counter/counter.sdc
+++ b/sdc-plugin/tests/counter/counter.sdc
@@ -1,2 +1,2 @@
-create_clock -period 10.0  -name clk2 -waveform {0.000 5.000} clk_int_1
-create_clock -period 10.0 -name clk -waveform {0.000 5.000} clk
+create_clock -period 10.0 -waveform {0.000 5.000} clk_int_1
+create_clock -period 10.0 -name clk -waveform {0.000 5.000} clk clk2
diff --git a/sdc-plugin/tests/counter/counter.v b/sdc-plugin/tests/counter/counter.v
index 70e02f5..2b671bb 100644
--- a/sdc-plugin/tests/counter/counter.v
+++ b/sdc-plugin/tests/counter/counter.v
@@ -1,16 +1,14 @@
 module top(input clk,
+        input clk2,
 	input [1:0] in,
-	output [4:0] out );
+	output [5:0] out );
 
 reg [1:0] cnt = 0;
-//wire [4:1] out;
 wire clk_int_1, clk_int_2;
 IBUF ibuf_proxy(.I(clk), .O(ibuf_proxy_out));
 IBUF ibuf_inst(.I(ibuf_proxy_out), .O(ibuf_out));
-//IBUF ibuf_inst_2(.I(ibuf_out_1), .O(ibuf_out_2));
 assign clk_int_1 = ibuf_out;
 assign clk_int_2 = clk_int_1;
-//assign do = out[0];
 
 always @(posedge clk_int_2) begin
 	cnt <= cnt + 1;
@@ -19,6 +17,7 @@
 middle middle_inst_1(.clk(ibuf_out), .out(out[2]));
 middle middle_inst_2(.clk(clk_int_1), .out(out[3]));
 middle middle_inst_3(.clk(clk_int_2), .out(out[4]));
+middle middle_inst_4(.clk(clk2), .out(out[5]));
 
 assign out[1:0] = {cnt[0], in[0]};
 endmodule