SDC: Add TODO comment to remove dangling wire check
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
diff --git a/sdc-plugin/propagation.cc b/sdc-plugin/propagation.cc
index 1982aef..460efbf 100644
--- a/sdc-plugin/propagation.cc
+++ b/sdc-plugin/propagation.cc
@@ -248,6 +248,8 @@
for (auto output : Pll::outputs) {
RTLIL::Wire* wire = FindSinkWireOnPort(cell, output);
// Don't add clocks on dangling wires
+ // TODO Remove the workaround with the WireHasSinkCell check once the following issue is fixed:
+ // https://github.com/SymbiFlow/yosys-symbiflow-plugins/issues/59
if (wire && WireHasSinkCell(wire)) {
float clkout_period(pll.clkout_period.at(output));
float clkout_rising_edge(pll.clkout_rising_edge.at(output));
