SDC: Add test for pll with propagated clocks
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
diff --git a/sdc-plugin/tests/Makefile b/sdc-plugin/tests/Makefile
index 56525df..503c542 100644
--- a/sdc-plugin/tests/Makefile
+++ b/sdc-plugin/tests/Makefile
@@ -14,6 +14,7 @@
pll_fbout_phase \
pll_approx_equal \
pll_dangling_wires \
+ pll_propagated \
set_false_path \
set_max_delay \
set_clock_groups \
@@ -34,6 +35,7 @@
pll_fbout_phase_verify = $(call diff_test,pll_fbout_phase,sdc)
pll_approx_equal_verify = $(call diff_test,pll_approx_equal,sdc)
pll_dangling_wires_verify = $(call diff_test,pll_dangling_wires,sdc)
+pll_propagated_verify = $(call diff_test,pll_propagated,sdc)
set_false_path_verify = $(call diff_test,set_false_path,sdc)
set_max_delay_verify = $(call diff_test,set_max_delay,sdc)
set_clock_groups_verify = $(call diff_test,set_clock_groups,sdc)
diff --git a/sdc-plugin/tests/pll_propagated/pll_propagated.golden.sdc b/sdc-plugin/tests/pll_propagated/pll_propagated.golden.sdc
new file mode 100644
index 0000000..5f1fc75
--- /dev/null
+++ b/sdc-plugin/tests/pll_propagated/pll_propagated.golden.sdc
@@ -0,0 +1,8 @@
+create_clock -period 10 -waveform {0 5} \$auto\$clkbufmap.cc:262:execute\$1715
+create_clock -period 10 -waveform {2.5 7.5} \$auto\$clkbufmap.cc:262:execute\$1717
+create_clock -period 2.5 -waveform {0 1.25} \$auto\$clkbufmap.cc:262:execute\$1719
+create_clock -period 5 -waveform {1.25 3.75} \$auto\$clkbufmap.cc:262:execute\$1721
+create_clock -period 10 -waveform {0 5} \$techmap1617\FDCE_0.C
+create_clock -period 10 -waveform {2.5 7.5} main_clkout0
+create_clock -period 2.5 -waveform {0 1.25} main_clkout1
+create_clock -period 5 -waveform {1.25 3.75} main_clkout2
diff --git a/sdc-plugin/tests/pll_propagated/pll_propagated.input.sdc b/sdc-plugin/tests/pll_propagated/pll_propagated.input.sdc
new file mode 100644
index 0000000..00354d7
--- /dev/null
+++ b/sdc-plugin/tests/pll_propagated/pll_propagated.input.sdc
@@ -0,0 +1 @@
+create_clock -period 10 -waveform {0 5} clk
diff --git a/sdc-plugin/tests/pll_propagated/pll_propagated.tcl b/sdc-plugin/tests/pll_propagated/pll_propagated.tcl
new file mode 100644
index 0000000..a321aeb
--- /dev/null
+++ b/sdc-plugin/tests/pll_propagated/pll_propagated.tcl
@@ -0,0 +1,21 @@
+yosys -import
+plugin -i sdc
+# Import the commands from the plugins to the tcl interpreter
+yosys -import
+
+read_verilog $::env(DESIGN_TOP).v
+read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
+read_verilog -lib +/xilinx/cells_xtra.v
+hierarchy -check -auto-top
+
+# Start flow after library reading
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+
+# Read the design timing constraints
+read_sdc $::env(DESIGN_TOP).input.sdc
+
+# Propagate the clocks
+propagate_clocks
+
+# Write out the SDC file after the clock propagation step
+write_sdc -include_propagated_clocks $::env(DESIGN_TOP).sdc
diff --git a/sdc-plugin/tests/pll_propagated/pll_propagated.v b/sdc-plugin/tests/pll_propagated/pll_propagated.v
new file mode 100644
index 0000000..63542da
--- /dev/null
+++ b/sdc-plugin/tests/pll_propagated/pll_propagated.v
@@ -0,0 +1,91 @@
+module top(
+ input clk,
+ input cpu_reset,
+ input data_in,
+ output[5:0] data_out
+);
+
+wire [5:0] data_out;
+wire builder_pll_fb;
+wire fdce_0_out, fdce_1_out;
+wire main_locked;
+
+FDCE FDCE_0 (
+ .D(data_in),
+ .C(clk),
+ .CE(1'b1),
+ .CLR(1'b0),
+ .Q(fdce_0_out)
+);
+
+FDCE FDCE_1 (
+ .D(fdce_0_out),
+ .C(clk),
+ .CE(1'b1),
+ .CLR(1'b0),
+ .Q(data_out[0])
+);
+
+PLLE2_ADV #(
+ .CLKFBOUT_MULT(4'd12),
+ .CLKIN1_PERIOD(10.0),
+ .CLKOUT0_DIVIDE(4'd12),
+ .CLKOUT0_PHASE(90.0),
+ .CLKOUT1_DIVIDE(2'd3),
+ .CLKOUT1_PHASE(0.0),
+ .CLKOUT2_DIVIDE(3'd6),
+ .CLKOUT2_PHASE(90.0),
+ .DIVCLK_DIVIDE(1'd1),
+ .REF_JITTER1(0.01),
+ .STARTUP_WAIT("FALSE")
+) PLLE2_ADV (
+ .CLKFBIN(builder_pll_fb),
+ .CLKIN1(clk),
+ .RST(cpu_reset),
+ .CLKFBOUT(builder_pll_fb),
+ .CLKOUT0(main_clkout0),
+ .CLKOUT1(main_clkout1),
+ .CLKOUT2(main_clkout2),
+ .LOCKED(main_locked)
+);
+
+FDCE FDCE_PLLx1_PH90 (
+ .D(data_in),
+ .C(main_clkout0),
+ .CE(1'b1),
+ .CLR(1'b0),
+ .Q(data_out[1])
+);
+
+FDCE FDCE_PLLx4_PH0_0 (
+ .D(data_in),
+ .C(main_clkout1),
+ .CE(1'b1),
+ .CLR(1'b0),
+ .Q(data_out[2])
+);
+
+FDCE FDCE_PLLx4_PH0_1 (
+ .D(data_in),
+ .C(main_clkout1),
+ .CE(1'b1),
+ .CLR(1'b0),
+ .Q(data_out[3])
+);
+
+FDCE FDCE_PLLx4_PH0_2 (
+ .D(data_in),
+ .C(main_clkout1),
+ .CE(1'b1),
+ .CLR(1'b0),
+ .Q(data_out[4])
+);
+
+FDCE FDCE_PLLx2_PH90_0 (
+ .D(data_in),
+ .C(main_clkout2),
+ .CE(1'b1),
+ .CLR(1'b0),
+ .Q(data_out[5])
+);
+endmodule
