)]}'
{
  "commit": "1ed0625181b237b7a7ca61b07b5d6c924ce29153",
  "tree": "33819523fb4a22f1f2ea917bbf5783c0aab95183",
  "parents": [
    "42cdb06022587d2723a3aae4581fe08e7adaeaee"
  ],
  "author": {
    "name": "Magdalena Andrys",
    "email": "mandrys@antmicro.com",
    "time": "Thu Nov 03 13:05:03 2022 +0100"
  },
  "committer": {
    "name": "Magdalena Andrys",
    "email": "mandrys@antmicro.com",
    "time": "Fri Nov 04 11:50:34 2022 +0100"
  },
  "message": "systemverilog: Support binary bitwise NAND and NOR\n\nBinary bitwise NAND and NOR are modeled in Surelog\nas bitwise reduction operations with two operands,\nso they need to be re-interpreted as binary bitwise\noperations by the plugin.\n\nSigned-off-by: Magdalena Andrys \u003cmandrys@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6790fe923124a8e10d0953cb3b3cdc9fd3b967f4",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "73902f14b98f9468b2d3fec573447d7a5ee78e67",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}