)]}'
{
  "commit": "20a9495624935a1768df07e15c9a80abb8630d00",
  "tree": "752d6c35e35eb514201ee23d57fbaca40cdbf36e",
  "parents": [
    "c14110b97d311d83047a9424fcc4aba49ddff6c2"
  ],
  "author": {
    "name": "Wojciech Sipak",
    "email": "wsipak@antmicro.com",
    "time": "Tue May 23 13:39:31 2023 +0200"
  },
  "committer": {
    "name": "Wojciech Sipak",
    "email": "wsipak@antmicro.com",
    "time": "Wed May 31 12:22:16 2023 +0200"
  },
  "message": "allow multiple ranges in dot notation\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8e4b4c56d73a04daeda5e3733d7b8b6e21129881",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "4083df0f324183b9ffea2d4c67f36362eade9241",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}