)]}'
{
  "commit": "24755e3b43400ad25e90fe01cc764a28a12de999",
  "tree": "c843c35149ebd6264ed5678e6e4b88597896eea7",
  "parents": [
    "35a3c3c2e4e85d08cc40713346bb296f1a0e44d1",
    "3c86f71b1bd0533960004a6be783a6dbd0667940"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue Mar 07 15:44:51 2023 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Mar 07 15:44:51 2023 +0100"
  },
  "message": "Merge pull request #464 from antmicro/kr/negative_range\n\nsystemverilog-plugin: set range before range_valid",
  "tree_diff": []
}