tree c843c35149ebd6264ed5678e6e4b88597896eea7
parent 35a3c3c2e4e85d08cc40713346bb296f1a0e44d1
parent 3c86f71b1bd0533960004a6be783a6dbd0667940
author Kamil Rakoczy <krakoczy@antmicro.com> 1678200291 +0100
committer GitHub <noreply@github.com> 1678200291 +0100
gpgsig -----BEGIN PGP SIGNATURE-----
 
 wsBcBAABCAAQBQJkB03jCRBK7hj4Ov3rIwAA/1kIABTeb4gGFwGmF6pwxrHrymQz
 7+RoTd9MGAYDYrCgPq+V/sPyq5IAqFxeq0/JbxDtQIPTtWhLY3hyr9dM/8+LbTUj
 svEkcf3DPwQZkzQcJ02MSpHVVb3pI/4zbuTQfka4dmxch494xVvmuG/QN+zSV634
 eEANAsOnH2Zh/P/MtjMHpggdxZ1V4b2i9SXbi8Q0gc+iZPQSvvjANvOc3QEucc1k
 Nx5vXGzal4xyn4hoU/sziaVjQOhidfHJZFhoVqs8Droq+fS7lskgSEEQBxh1lRaa
 sLv7Z1qazDzPM5DVFEodjwOpx03p61DtJkZOS07VWe02pr7fKnK7r2wLHZ/fCxM=
 =hyST
 -----END PGP SIGNATURE-----
 

Merge pull request #464 from antmicro/kr/negative_range

systemverilog-plugin: set range before range_valid