)]}'
{
  "commit": "26c42657d6846cba7c2b4d664905068d27722dd3",
  "tree": "7469ac32630a0a415b557b89fc7ef8fa1a5edfbc",
  "parents": [
    "02bc3f77485567f53f1639a0bd16e715c280bd92"
  ],
  "author": {
    "name": "Rafal Kapuscik",
    "email": "rkapuscik@antmicro.com",
    "time": "Tue Oct 11 11:38:03 2022 +0200"
  },
  "committer": {
    "name": "Rafal Kapuscik",
    "email": "rkapuscik@antmicro.com",
    "time": "Tue Oct 11 11:41:05 2022 +0200"
  },
  "message": "Correctly annotate signed ports\n\nSigned-off-by: Rafal Kapuscik \u003crkapuscik@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "55acd25781f0e0afed905d46e6a652d1e888bfcb",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "fb51baf072aacb18e1c0350b8e238476a796f8a3",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}