| commit | 7e5557259154c2fcd72c3a29cd2f20f8666106cf | [log] [tgz] |
|---|---|---|
| author | Henner Zeller <h.zeller@acm.org> | Wed Mar 17 15:43:37 2021 -0700 |
| committer | Henner Zeller <h.zeller@acm.org> | Wed Mar 17 15:45:20 2021 -0700 |
| tree | cbe2d7fae29d0a8b2c5d91934b384597e6b76d3a | |
| parent | ac47a745ac2783cd97375683e7b6762890789179 [diff] |
Add formatting option for verilog files. Make this a separate format-verilog target for now, as not everyone has verible installed and there are a few files that it can't format (the \$_BUF_ stuff in particular). Simplify double-line format call with single line for c++ formatting. Set editorconfig to the standard indentation according to styleguide. Signed-off-by: Henner Zeller <h.zeller@acm.org>
This repository contains plugins for Yosys developed as part of the SymbiFlow project.
Adds several commands that allow for collecting information about cells, nets, pins and ports in the design or a selection of objects. Additionally provides functions to convert selection on TCL lists.
Following commands are added with the plugin:
Writes out the design's fasm features based on the parameter annotations on a design cell.
The plugin adds the following command:
Implements a pass that integrates inverters into cells that have ports with the ‘invertible_pin’ attribute set.
The plugin adds the following command:
Reads the specified parameter on a selected object.
The plugin adds the following command:
QL IOB plugin annotates IO buffer cells with information from IO placement constraints.
The plugin adds the following command:
Reads Standard Delay Format (SDC) constraints, propagates these constraints across the design and writes out the complete SDC information.
The plugin adds the following commands:
Reads Xilinx Design Constraints (XDC) files and annotates the specified cells parameters with properties such as:
The plugin adds the following commands: