)]}'
{
  "commit": "2ec0e35c3ff9c2a2379ce5c802af52bd556f8d09",
  "tree": "9f780951c49a0da1fc56f4bcf94e9773cb974e2f",
  "parents": [
    "f527ced01234b3af9deaef4e2f745ea9a4fb7919",
    "7d274244e5f1b98ab440be1a74c2ec8b81a9bdb4"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue May 16 12:22:11 2023 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue May 16 12:22:11 2023 +0200"
  },
  "message": "Merge pull request #512 from antmicro/kr/change_remove_message\n\nsystemverilog-plugin: update remove module message",
  "tree_diff": []
}