commit 2fa356d11c8296d25f90ec6690cd889efaa29f82
author Rafal Kapuscik <54976862+rkapuscik@users.noreply.github.com> Thu May 12 14:39:10 2022 +0200
committer GitHub <noreply@github.com> Thu May 12 14:39:10 2022 +0200
tree 91541dafef0ee17068138d3971c4a9d955e41c4c
parent bad008e97a621c78ab2a5056fb22b8130012a3c4
parent 0308bdb0a18f3cff0ef475f84798e625b86deaf3

Merge pull request #319 from antmicro/function-ranges

Fix logic var ranges access

systemverilog-plugin/UhdmAst.cc

diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index be3d3c0..978fde5 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -1717,6 +1717,18 @@
         shared.report.mark_handled(typespec_h);
         break;
     }
+    case vpiByteTypespec: {
+        current_node->is_signed = true;
+        packed_ranges.push_back(make_range(7, 0));
+        shared.report.mark_handled(typespec_h);
+        break;
+    }
+    case vpiShortIntTypespec: {
+        current_node->is_signed = true;
+        packed_ranges.push_back(make_range(15, 0));
+        shared.report.mark_handled(typespec_h);
+        break;
+    }
     case vpiIntTypespec:
     case vpiIntegerTypespec: {
         current_node->is_signed = true;
@@ -3398,7 +3410,17 @@
     std::vector<AST::AstNode *> packed_ranges;   // comes before wire name
     std::vector<AST::AstNode *> unpacked_ranges; // comes after wire name
     current_node = make_ast_node(AST::AST_WIRE);
-    packed_ranges.push_back(make_range(16, 0));
+    packed_ranges.push_back(make_range(15, 0));
+    add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
+    current_node->is_signed = true;
+}
+
+void UhdmAst::process_byte_typespec()
+{
+    std::vector<AST::AstNode *> packed_ranges;   // comes before wire name
+    std::vector<AST::AstNode *> unpacked_ranges; // comes after wire name
+    current_node = make_ast_node(AST::AST_WIRE);
+    packed_ranges.push_back(make_range(7, 0));
     add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
     current_node->is_signed = true;
 }
@@ -3408,7 +3430,7 @@
     std::vector<AST::AstNode *> packed_ranges;   // comes before wire name
     std::vector<AST::AstNode *> unpacked_ranges; // comes after wire name
     current_node = make_ast_node(AST::AST_WIRE);
-    packed_ranges.push_back(make_range(64, 0));
+    packed_ranges.push_back(make_range(63, 0));
     add_multirange_wire(current_node, packed_ranges, unpacked_ranges);
     current_node->is_signed = false;
 }
@@ -3675,6 +3697,11 @@
             shared.report.mark_handled(typespec_h);
             break;
         }
+        case vpiByteTypespec: {
+            packed_ranges.push_back(make_range(7, 0));
+            shared.report.mark_handled(typespec_h);
+            break;
+        }
         case vpiEnumTypespec:
         case vpiRealTypespec:
         case vpiStringTypespec: {
@@ -3701,6 +3728,7 @@
             });
             break;
         }
+        case vpiPackedArrayTypespec:
         case vpiArrayTypespec: {
             shared.report.mark_handled(typespec_h);
             visit_one_to_one({vpiElemTypespec}, typespec_h, [&](AST::AstNode *node) {
@@ -4055,6 +4083,9 @@
     case vpiBitTypespec:
         process_bit_typespec();
         break;
+    case vpiByteTypespec:
+        process_byte_typespec();
+        break;
     case vpiStringVar:
         process_string_var();
         break;

systemverilog-plugin/UhdmAst.h

diff --git a/systemverilog-plugin/UhdmAst.h b/systemverilog-plugin/UhdmAst.h
index 2add851..0314369 100644
--- a/systemverilog-plugin/UhdmAst.h
+++ b/systemverilog-plugin/UhdmAst.h
@@ -133,6 +133,7 @@
     void process_string_typespec();
     void process_repeat();
     void process_byte_var();
+    void process_byte_typespec();
     void process_long_int_var();
     void process_immediate_cover();
     void process_immediate_assume();