diff --git a/sdc-plugin/tests/get_clocks/get_clocks.tcl b/sdc-plugin/tests/get_clocks/get_clocks.tcl
index 10758b1..6f0eea7 100644
--- a/sdc-plugin/tests/get_clocks/get_clocks.tcl
+++ b/sdc-plugin/tests/get_clocks/get_clocks.tcl
@@ -9,7 +9,8 @@
 read_verilog -lib +/xilinx/cells_xtra.v
 hierarchy -check -auto-top
 # Start flow after library reading
-synth_xilinx -vpr -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+#synth_xilinx
 
 # Read the design's timing constraints
 read_sdc $::env(DESIGN_TOP).input.sdc