Merge pull request #271 from antmicro/pcza/ql-qlf-k6n10f-sdp-inference
ql-qlf: k6n10f: Add SDP RAM inference
diff --git a/ql-qlf-plugin/qlf_k6n10f/arith_map.v b/ql-qlf-plugin/qlf_k6n10f/arith_map.v
index 25c6901..c5dd221 100644
--- a/ql-qlf-plugin/qlf_k6n10f/arith_map.v
+++ b/ql-qlf-plugin/qlf_k6n10f/arith_map.v
@@ -9,9 +9,9 @@
module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
- parameter A_WIDTH = 1;
- parameter B_WIDTH = 1;
- parameter Y_WIDTH = 1;
+ parameter A_WIDTH = 2;
+ parameter B_WIDTH = 2;
+ parameter Y_WIDTH = 2;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
@@ -40,14 +40,15 @@
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
genvar i;
+ wire co;
(* force_downto *)
//wire [Y_WIDTH-1:0] C = {CO, CI};
wire [Y_WIDTH:0] C;
(* force_downto *)
wire [Y_WIDTH-1:0] S = {AA ^ BB};
-
assign CO[Y_WIDTH-1:0] = C[Y_WIDTH:1];
+ //assign CO[Y_WIDTH-1] = co;
generate
adder_carry intermediate_adder (
@@ -59,7 +60,7 @@
);
endgenerate
genvar i;
- generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
+ generate for (i = 0; i < Y_WIDTH-2; i = i + 1) begin:slice
adder_carry my_adder (
.cin(C[i]),
.g(AA[i]),
@@ -68,6 +69,21 @@
.sumout(Y[i])
);
end endgenerate
+ generate
+ adder_carry final_adder (
+ .cin (C[Y_WIDTH-2]),
+ .cout (),
+ .p (1'b0),
+ .g (1'b0),
+ .sumout (co)
+ );
+ endgenerate
+
+ assign Y[Y_WIDTH-2] = S[Y_WIDTH-2] ^ co;
+ assign C[Y_WIDTH-1] = S[Y_WIDTH-2] ? co : AA[Y_WIDTH-2];
+ assign Y[Y_WIDTH-1] = S[Y_WIDTH-1] ^ C[Y_WIDTH-1];
+ assign C[Y_WIDTH] = S[Y_WIDTH-1] ? C[Y_WIDTH-1] : AA[Y_WIDTH-1];
+
assign X = S;
endmodule
diff --git a/ql-qlf-plugin/tests/full_adder/full_adder.tcl b/ql-qlf-plugin/tests/full_adder/full_adder.tcl
index 41443f4..deef6b5 100644
--- a/ql-qlf-plugin/tests/full_adder/full_adder.tcl
+++ b/ql-qlf-plugin/tests/full_adder/full_adder.tcl
@@ -68,7 +68,7 @@
design -load postopt
yosys cd full_adder
stat
-select -assert-count 6 t:adder_carry
+select -assert-count 5 t:adder_carry
design -reset
@@ -80,7 +80,7 @@
design -load postopt
yosys cd subtractor
stat
-select -assert-count 6 t:adder_carry
+select -assert-count 5 t:adder_carry
design -reset
@@ -92,7 +92,7 @@
design -load postopt
yosys cd comparator
stat
-select -assert-count 5 t:adder_carry
+select -assert-count 4 t:adder_carry
design -reset
diff --git a/uhdm-plugin/uhdmsurelogastfrontend.cc b/uhdm-plugin/uhdmsurelogastfrontend.cc
index ce79772..4828896 100644
--- a/uhdm-plugin/uhdmsurelogastfrontend.cc
+++ b/uhdm-plugin/uhdmsurelogastfrontend.cc
@@ -78,6 +78,7 @@
}
struct UhdmSurelogAstFrontend : public UhdmCommonFrontend {
+ UhdmSurelogAstFrontend(std::string name, std::string short_help) : UhdmCommonFrontend(name, short_help) {}
UhdmSurelogAstFrontend() : UhdmCommonFrontend("verilog_with_uhdm", "generate/read UHDM file") {}
void print_read_options() override
{
@@ -110,6 +111,12 @@
if (!success) {
log_error("Error parsing Surelog arguments!\n");
}
+ // Force -parse flag settings even if it wasn't specified
+ clp->setwritePpOutput(true);
+ clp->setParse(true);
+ clp->setCompile(true);
+ clp->setElaborate(true);
+
SURELOG::scompiler *compiler = nullptr;
const std::vector<vpiHandle> uhdm_design = executeCompilation(symbolTable, errors, clp, compiler);
@@ -129,4 +136,8 @@
void call_log_header(RTLIL::Design *design) override { log_header(design, "Executing Verilog with UHDM frontend.\n"); }
} UhdmSurelogAstFrontend;
+struct UhdmSystemVerilogFrontend : public UhdmSurelogAstFrontend {
+ UhdmSystemVerilogFrontend() : UhdmSurelogAstFrontend("systemverilog", "read SystemVerilog files") {}
+} UhdmSystemVerilogFrontend;
+
YOSYS_NAMESPACE_END
