commit 3327d62c23897ec9fb935e9d433038003ce4364c
author Rafal Kapuscik <rkapuscik@antmicro.com> Fri Mar 18 12:47:51 2022 +0100
committer Rafal Kapuscik <rkapuscik@antmicro.com> Wed Mar 23 14:09:47 2022 +0100
tree 022da70aeb8915d05d4da72e6d309e9a0d8a378c
parent 400824259d7d2cd499dcd27a4f20e10913b5630e

Mark empty range as valid

This allows usage of imported identifiers in operations inside signal
access.

Signed-off-by: Rafal Kapuscik <rkapuscik@antmicro.com>

systemverilog-plugin/UhdmAst.cc

diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index f461e17..3f6f148 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -406,6 +406,7 @@
     if (packed_ranges.empty() && unpacked_ranges.empty()) {
         wire_node->attributes.erase(UhdmAst::packed_ranges());
         wire_node->attributes.erase(UhdmAst::unpacked_ranges());
+        wire_node->range_valid = true;
         return;
     }
     size_t size = 1;