diff --git a/ql-qlf-plugin/pp3/brams_map.v b/ql-qlf-plugin/pp3/brams_map.v
index 1941a3d..ded9343 100644
--- a/ql-qlf-plugin/pp3/brams_map.v
+++ b/ql-qlf-plugin/pp3/brams_map.v
@@ -35,8 +35,8 @@
   input [CFG_DBITS-1:0] B1DATA;
   input [CFG_ENABLE_B-1:0] B1EN;
 
-  assign VCC = 1'b1;
-  assign GND = 1'b0;
+  wire VCC = 1'b1;
+  wire GND = 1'b0;
 
   wire [3:0] DIP, DOP;
   wire [31:0] DI, DO;
@@ -259,8 +259,8 @@
   assign wen_reg[2:CFG_ENABLE_B] = 0;
   assign wen_reg[CFG_ENABLE_B-1:0] = B1EN;
 
-  assign GND = 1'b0;
-  assign VCC = 1'b1;
+  wire GND = 1'b0;
+  wire VCC = 1'b1;
 
   assign A1DATA = DO;
   assign DI = B1DATA;
@@ -547,7 +547,7 @@
       .RMEB(GND)
   );
 
-  assign RD[data_width_int-1 : 0] = out_reg0[data_width_int-1 : 0];
+  assign RD[data_width_int-1 : 0] = {out_par0, out_reg0};
 
 endmodule
 
@@ -825,7 +825,7 @@
 
   endgenerate
 
-  assign RD[data_width_int-1 : 0] = out_reg0[data_width_int-1 : 0];
+  assign RD[data_width_int-1 : 0] = {out_par0, out_reg0};
 
 endmodule
 
@@ -849,7 +849,7 @@
     DOUT
 );
 
-  parameter data_depth_int = 512, data_width_int = 36, reg_rd_int = 0, sync_fifo_int = 0;
+  parameter data_depth_int = 512, data_width_int = 18, reg_rd_int = 0, sync_fifo_int = 0;
 
   input Fifo_Push_Flush, Fifo_Pop_Flush;
   input Push_Clk, Pop_Clk;
@@ -1002,7 +1002,7 @@
       .RMEB(GND)
   );
 
-  assign DOUT[data_width_int-1 : 0] = out_reg0[data_width_int-1 : 0];
+  assign DOUT[data_width_int-1 : 0] = {out_par0, out_reg0};
 
 endmodule
 
@@ -1255,6 +1255,6 @@
 
   endgenerate
 
-  assign DOUT[data_width_int-1 : 0] = out_reg0[data_width_int-1 : 0];
+  assign DOUT[data_width_int-1 : 0] = {out_par0, out_reg0};
 
 endmodule
diff --git a/ql-qlf-plugin/synth_quicklogic.cc b/ql-qlf-plugin/synth_quicklogic.cc
index 36c3afe..241005d 100644
--- a/ql-qlf-plugin/synth_quicklogic.cc
+++ b/ql-qlf-plugin/synth_quicklogic.cc
@@ -192,7 +192,10 @@
             std::string readVelArgs;
             readVelArgs = " +/quicklogic/" + family + "/cells_sim.v";
 
-            run("read_verilog -lib -specify +/quicklogic/common/cells_sim.v" + readVelArgs);
+            // Use -nomem2reg here to prevent Yosys from complaining about
+            // some block ram cell models. After all the only part of the cells
+            // library required here is cell port definitions plus specify blocks.
+            run("read_verilog -lib -specify -nomem2reg +/quicklogic/common/cells_sim.v" + readVelArgs);
             run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
         }