)]}'
{
  "commit": "345fe14ee26f9de64170fffb00d7229ac6fe1864",
  "tree": "80fec06460d32501854cdb3804c582e919507c51",
  "parents": [
    "08430ec4f53d1cf9d6a2091211d6c5ce501d5486",
    "1124b5328185a3edc5f3b03b7d4c88cb872af138"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Mon Feb 13 16:49:38 2023 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon Feb 13 16:49:38 2023 +0100"
  },
  "message": "Merge pull request #452 from antmicro/kr/add_list_op\n\nsystemverilog-plugin: move handle of list op to process_case_item",
  "tree_diff": []
}