)]}'
{
  "commit": "35a3c3c2e4e85d08cc40713346bb296f1a0e44d1",
  "tree": "73615f1162d4c7ee0897d985b3f5a0a6455dff3e",
  "parents": [
    "ab3e14fbc69bcc8f0575437b51a76d85f7d19c82",
    "8430e6469f44993a53cfc5ac80952d50d8d946bf"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Mon Mar 06 14:53:55 2023 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon Mar 06 14:53:55 2023 +0100"
  },
  "message": "Merge pull request #462 from antmicro/kr/wire_fix\n\nsystemverilog-plugin: fix wires not starting from 0",
  "tree_diff": []
}