tree 73615f1162d4c7ee0897d985b3f5a0a6455dff3e
parent ab3e14fbc69bcc8f0575437b51a76d85f7d19c82
parent 8430e6469f44993a53cfc5ac80952d50d8d946bf
author Kamil Rakoczy <krakoczy@antmicro.com> 1678110835 +0100
committer GitHub <noreply@github.com> 1678110835 +0100
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Merge pull request #462 from antmicro/kr/wire_fix

systemverilog-plugin: fix wires not starting from 0