)]}'
{
  "commit": "36150950dcf2acf47af719008ec33c055a0b4bab",
  "tree": "0f48176c7f4a82e8080f9c352ddc2f0774a20859",
  "parents": [
    "dfc1b7320867185427b21e16183d6075ea8fcd18"
  ],
  "author": {
    "name": "Robert Szczepanski",
    "email": "rszczepanski@antmicro.com",
    "time": "Tue Jan 03 14:23:17 2023 +0100"
  },
  "committer": {
    "name": "Robert Szczepanski",
    "email": "rszczepanski@antmicro.com",
    "time": "Tue Jan 03 14:23:48 2023 +0100"
  },
  "message": "systemverilog: Fix resolving interface members\u0027 types\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8f92ac6d1a5b922698689dd8ce51f7fe634fe2ac",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "1c62f28e2cf4cdf73ef552bdb4d711b3944055cd",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}