)]}'
{
  "commit": "382aabfc436fe6496c32e685143081ab376a6982",
  "tree": "9a85594814232058a1318bfab56895d027ae4a94",
  "parents": [
    "94d267daca1eb0cc80c97c420f3138144d2490b8"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Wed Apr 05 14:01:05 2023 +0200"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue Apr 11 10:37:43 2023 +0200"
  },
  "message": "systemverilog-plugin: fix sometimes wrong handle of ranges in port wire\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "febcb9d154a05b41b615d7278609d5701258e29f",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "1d9689e5b653bb10392f6757686c9dc5fa47f5b3",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}