)]}'
{
  "commit": "38a8a5dd5a7bb880e1dbcbcb14e97d6e9917da3d",
  "tree": "2ff3a4106435058881ef1a36811f8db8dc8f1721",
  "parents": [
    "730146f49eeae9021d31fae0f39b1e3568879b44",
    "f85cd18a3593e50c1079cd492691a54aa96fb878"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Fri May 19 09:23:42 2023 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri May 19 09:23:42 2023 +0200"
  },
  "message": "Merge pull request #518 from antmicro/kr/split_line_column\n\nsystemverilog-plugin: split line and column in uhdmast_assert_log",
  "tree_diff": []
}