| commit | 56efb7460aef981788b35bbba6be108632337eec | [log] [tgz] |
|---|---|---|
| author | Tomasz Michalak <tmichalak@antmicro.com> | Thu Sep 10 17:28:21 2020 +0200 |
| committer | Tomasz Michalak <tmichalak@antmicro.com> | Tue Sep 15 16:35:26 2020 +0200 |
| tree | 4ed682f4de35e4437320483a239bf0e707c8f7dd | |
| parent | e5a04f5f8499ef2252d8e8d58c2e75fce717cde5 [diff] |
SDC: Add duty cycle and input clock delay to output clock Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
This repository contains plugins for Yosys developed as part of the SymbiFlow project.