)]}'
{
  "commit": "3bfd4016e2a4bf32a37dac31ecae40e14e92474c",
  "tree": "2cbc62201ec945d3ff62c8802dd98c45513a5be8",
  "parents": [
    "cbd00f0cec6e966f6ad73936dea857b8e68f8ae3",
    "4ea2ebf5e47acaabeb41a26e089d740c80e9d889"
  ],
  "author": {
    "name": "Mariusz Glebocki",
    "email": "mglebocki@antmicro.com",
    "time": "Tue Apr 04 17:51:45 2023 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Apr 04 17:51:45 2023 +0200"
  },
  "message": "Merge pull request #471 from antmicro/kr/fix_param_const_simplify\n\nsystemverilog-plugin: fix calculate parameter value that requires extended simplify",
  "tree_diff": []
}