commit 3c86f71b1bd0533960004a6be783a6dbd0667940
author Kamil Rakoczy <krakoczy@antmicro.com> Mon Mar 06 11:42:04 2023 +0100
committer Kamil Rakoczy <krakoczy@antmicro.com> Mon Mar 06 11:42:04 2023 +0100
tree 4a0238c882b5ef448bbbb7e7f77aa376c052c0c2
parent ab3e14fbc69bcc8f0575437b51a76d85f7d19c82

systemverilog-plugin: set range before range_valid

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>

systemverilog-plugin/UhdmAst.cc

diff --git a/systemverilog-plugin/UhdmAst.cc b/systemverilog-plugin/UhdmAst.cc
index 0b465f0..5b059ef 100644
--- a/systemverilog-plugin/UhdmAst.cc
+++ b/systemverilog-plugin/UhdmAst.cc
@@ -511,6 +511,8 @@
     if (packed_ranges.empty() && unpacked_ranges.empty()) {
         wire_node->attributes.erase(UhdmAst::packed_ranges());
         wire_node->attributes.erase(UhdmAst::unpacked_ranges());
+        wire_node->range_left = 0;
+        wire_node->range_right = 0;
         wire_node->range_valid = true;
         return;
     }