)]}'
{
  "commit": "3c86f71b1bd0533960004a6be783a6dbd0667940",
  "tree": "4a0238c882b5ef448bbbb7e7f77aa376c052c0c2",
  "parents": [
    "ab3e14fbc69bcc8f0575437b51a76d85f7d19c82"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Mon Mar 06 11:42:04 2023 +0100"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Mon Mar 06 11:42:04 2023 +0100"
  },
  "message": "systemverilog-plugin: set range before range_valid\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0b465f0b64d75c8515bf96b8e10998f4a3d4f9ff",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "5b059ef52c6543041d0f3cd1b6c0cffb10b467ce",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}