add support for k6n10 factor family
Signed-off-by: Tarachand Pagarani <tpagarani@quicklogic.com>
diff --git a/ql-qlf-plugin/Makefile b/ql-qlf-plugin/Makefile
index e2fa3e1..4919037 100644
--- a/ql-qlf-plugin/Makefile
+++ b/ql-qlf-plugin/Makefile
@@ -18,6 +18,7 @@
COMMON = common
QLF_K4N8_DIR = qlf_k4n8
QLF_K6N10_DIR = qlf_k6n10
+QLF_K6N10F_DIR = qlf_k6n10f
PP3_DIR = pp3
VERILOG_MODULES = $(COMMON)/cells_sim.v \
$(QLF_K4N8_DIR)/arith_map.v \
@@ -30,6 +31,13 @@
$(QLF_K6N10_DIR)/ffs_map.v \
$(QLF_K6N10_DIR)/dsp_map.v \
$(QLF_K6N10_DIR)/lut_map.v \
+ $(QLF_K6N10F_DIR)/arith_map.v \
+ $(QLF_K6N10F_DIR)/brams_map.v \
+ $(QLF_K6N10F_DIR)/brams.txt \
+ $(QLF_K6N10F_DIR)/cells_sim.v \
+ $(QLF_K6N10F_DIR)/ffs_map.v \
+ $(QLF_K6N10F_DIR)/dsp_map.v \
+ $(QLF_K6N10F_DIR)/lut_map.v \
$(PP3_DIR)/abc9_map.v \
$(PP3_DIR)/abc9_model.v \
$(PP3_DIR)/abc9_unmap.v \
diff --git a/ql-qlf-plugin/qlf_k6n10f/arith_map.v b/ql-qlf-plugin/qlf_k6n10f/arith_map.v
new file mode 100644
index 0000000..c2323d6
--- /dev/null
+++ b/ql-qlf-plugin/qlf_k6n10f/arith_map.v
@@ -0,0 +1,70 @@
+// Copyright (C) 2020-2021 The SymbiFlow Authors.
+//
+// Use of this source code is governed by a ISC-style
+// license that can be found in the LICENSE file or at
+// https://opensource.org/licenses/ISC
+//
+// SPDX-License-Identifier:ISC
+(* techmap_celltype = "$alu" *)
+module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+ parameter _TECHMAP_CONSTVAL_CI_ = 0;
+ parameter _TECHMAP_CONSTMSK_CI_ = 0;
+
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] X, Y;
+
+ input CI, BI;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] CO;
+
+ wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+
+ genvar i;
+
+ (* force_downto *)
+ //wire [Y_WIDTH-1:0] C = {CO, CI};
+ wire [Y_WIDTH:0] C;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] S = {AA ^ BB};
+
+ generate
+ adder_carry intermediate_adder (
+ .cin ( ),
+ .cout (C[0]),
+ .p (1'b0),
+ .g (CI),
+ .sumout ()
+ );
+ endgenerate
+ genvar i;
+ generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
+ adder_carry my_adder (
+ .cin(C[i]),
+ .g(AA[i]),
+ .p(S[i]),
+ .cout(C[i+1]),
+ .sumout(Y[i])
+ );
+ end endgenerate
+ assign X = S;
+endmodule
+
diff --git a/ql-qlf-plugin/qlf_k6n10f/brams.txt b/ql-qlf-plugin/qlf_k6n10f/brams.txt
new file mode 100644
index 0000000..1664603
--- /dev/null
+++ b/ql-qlf-plugin/qlf_k6n10f/brams.txt
@@ -0,0 +1,64 @@
+
+bram $__QLF_FACTOR_BRAM36_TDP
+ init 1
+ abits 10 @a10d36
+ dbits 36 @a10d36
+ abits 11 @a11d18
+ dbits 18 @a11d18
+ abits 12 @a12d9
+ dbits 9 @a12d9
+ abits 13 @a13d4
+ dbits 4 @a13d4
+ abits 14 @a14d2
+ dbits 2 @a14d2
+ abits 15 @a15d1
+ dbits 1 @a15d1
+ groups 2
+ ports 1 1
+ wrmode 0 1
+ enable 1 4 @a10d36
+ enable 1 2 @a11d18
+ enable 1 1 @a12d9 @a13d4 @a14d2 @a15d1
+ transp 0 0
+ clocks 2 3
+ clkpol 2 3
+endbram
+
+bram $__QLF_FACTOR_BRAM18_TDP
+ init 1
+ abits 10 @a10d18
+ dbits 18 @a10d18
+ abits 11 @a11d9
+ dbits 9 @a11d9
+ abits 12 @a12d4
+ dbits 4 @a12d4
+ abits 13 @a13d2
+ dbits 2 @a13d2
+ abits 14 @a14d1
+ dbits 1 @a14d1
+ groups 2
+ ports 1 1
+ wrmode 0 1
+ enable 1 2 @a10d18
+ enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
+ transp 0 0
+ clocks 2 3
+ clkpol 2 3
+endbram
+
+
+match $__QLF_FACTOR_BRAM36_TDP
+ min bits 128
+ min efficiency 2
+ shuffle_enable B
+ make_transp
+ or_next_if_better
+endmatch
+
+match $__QLF_FACTOR_BRAM18_TDP
+ min bits 128
+ min efficiency 2
+ shuffle_enable B
+ make_transp
+endmatch
+
diff --git a/ql-qlf-plugin/qlf_k6n10f/brams_map.v b/ql-qlf-plugin/qlf_k6n10f/brams_map.v
new file mode 100644
index 0000000..be0b230
--- /dev/null
+++ b/ql-qlf-plugin/qlf_k6n10f/brams_map.v
@@ -0,0 +1,248 @@
+// Copyright (C) 2020-2021 The SymbiFlow Authors.
+//
+// Use of this source code is governed by a ISC-style
+// license that can be found in the LICENSE file or at
+// https://opensource.org/licenses/ISC
+//
+// SPDX-License-Identifier:ISC
+
+module \$__QLF_FACTOR_BRAM36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+ parameter CFG_ABITS = 10;
+ parameter CFG_DBITS = 36;
+ parameter CFG_ENABLE_B = 4;
+
+ parameter CLKPOL2 = 1;
+ parameter CLKPOL3 = 1;
+ parameter [36863:0] INIT = 36864'bx;
+
+ input CLK2;
+ input CLK3;
+
+ input [CFG_ABITS-1:0] A1ADDR;
+ output [CFG_DBITS-1:0] A1DATA;
+ input A1EN;
+
+ input [CFG_ABITS-1:0] B1ADDR;
+ input [CFG_DBITS-1:0] B1DATA;
+ input [CFG_ENABLE_B-1:0] B1EN;
+
+ wire [14:0] A1ADDR_15;
+ wire [14:0] B1ADDR_15;
+ //wire [7:0] B1EN_8 = //B1EN;
+
+ wire [3:0] DIP, DOP;
+ wire [31:0] DI, DO;
+
+ wire [31:0] DOBDO;
+ wire [3:0] DOPBDOP;
+
+ //wire [2:0] WRITEDATAWIDTHB;
+ //wire [2:0] READDATAWIDTHA;
+ assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
+ assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
+
+ assign A1ADDR_15[14:CFG_ABITS] = 0;
+ assign A1ADDR_15[CFG_ABITS-1:0] = A1ADDR;
+ assign B1ADDR_15[14:CFG_ABITS] = 0;
+ assign B1ADDR_15[CFG_ABITS-1:0] = B1ADDR;
+
+ /*if (CFG_DBITS == 1) begin
+ assign WRITEDATAWIDTHB = 3'b000;
+ assign READDATAWIDTHA = 3'b000;
+ end else if (CFG_DBITS == 2) begin
+ assign WRITEDATAWIDTHB = 3'b001;
+ assign READDATAWIDTHA = 3'b001;
+ end else if (CFG_DBITS > 2 && CFG_DBITS <= 4) begin
+ assign WRITEDATAWIDTHB = 3'b010;
+ assign READDATAWIDTHA = 3'b010;
+ end else if (CFG_DBITS > 4 && CFG_DBITS <= 9) begin
+ assign WRITEDATAWIDTHB = 3'b011;
+ assign READDATAWIDTHA = 3'b011;
+ end else if (CFG_DBITS > 9 && CFG_DBITS <= 18) begin
+ assign WRITEDATAWIDTHB = 3'b100;
+ assign READDATAWIDTHA = 3'b100;
+ end else if (CFG_DBITS > 18 && CFG_DBITS <= 36) begin
+ assign WRITEDATAWIDTHB = 3'b101;
+ assign READDATAWIDTHA = 3'b101;
+ end*/
+ generate if (CFG_DBITS > 8) begin
+ TDP_BRAM36 #(
+ //`include "brams_init_36.vh"
+ .READ_WIDTH_A(CFG_DBITS),
+ .READ_WIDTH_B(CFG_DBITS),
+ .WRITE_WIDTH_A(CFG_DBITS),
+ .WRITE_WIDTH_B(CFG_DBITS),
+ ) _TECHMAP_REPLACE_ (
+ .WRITEDATAA(32'hFFFFFFFF),
+ .WRITEDATAAP(4'hF),
+ .READDATAA(DO[31:0]),
+ .READDATAAP(DOP[3:0]),
+ .ADDRA(A1ADDR_15),
+ .CLOCKA(CLK2),
+ .READENABLEA(A1EN),
+ .WRITEENABLEA(1'b0),
+ .BYTEENABLEA(4'b0),
+ //.WRITEDATAWIDTHA(3'b0),
+ //.READDATAWIDTHA(READDATAWIDTHA),
+
+ .WRITEDATAB(DI),
+ .WRITEDATABP(DIP),
+ .READDATAB(DOBDO),
+ .READDATABP(DOPBDOP),
+ .ADDRB(B1ADDR_15),
+ .CLOCKB(CLK3),
+ .READENABLEA(1'b0),
+ .WRITEENABLEB(1'b1),
+ .BYTEENABLEB(B1EN)
+ //.WRITEDATAWIDTHB(WRITEDATAWIDTHB),
+ //.READDATAWIDTHB(3'b0)
+ );
+ end else begin
+ TDP_BRAM36 #(
+ //`include "brams_init_32.vh"
+ ) _TECHMAP_REPLACE_ (
+ .WRITEDATAA(32'hFFFFFFFF),
+ .WRITEDATAAP(4'hF),
+ .READDATAA(DO[31:0]),
+ .READDATAAP(DOP[3:0]),
+ .ADDRA(A1ADDR_15),
+ .CLOCKA(CLK2),
+ .READENABLEA(A1EN),
+ .WRITEENABLEA(1'b0),
+ .BYTEENABLEA(4'b0),
+ //.WRITEDATAWIDTHA(3'b0),
+ //.READDATAWIDTHA(READDATAWIDTHA),
+
+ .WRITEDATAB(DI),
+ .WRITEDATABP(DIP),
+ .READDATAB(DOBDO),
+ .READDATABP(DOPBDOP),
+ .ADDRB(B1ADDR_15),
+ .CLOCKB(CLK3),
+ .READENABLEB(1'b0),
+ .WRITEENABLEB(1'b1),
+ .BYTEENABLEB(B1EN)
+ //.WRITEDATAWIDTHB(WRITEDATAWIDTHB),
+ //.READDATAWIDTHB(3'b0)
+ );
+ end endgenerate
+endmodule
+
+// ------------------------------------------------------------------------
+
+module \$__QLF_FACTOR_BRAM18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+ parameter CFG_ABITS = 10;
+ parameter CFG_DBITS = 18;
+ parameter CFG_ENABLE_B = 2;
+
+ parameter CLKPOL2 = 1;
+ parameter CLKPOL3 = 1;
+ parameter [18431:0] INIT = 18432'bx;
+
+ input CLK2;
+ input CLK3;
+
+ input [CFG_ABITS-1:0] A1ADDR;
+ output [CFG_DBITS-1:0] A1DATA;
+ input A1EN;
+
+ input [CFG_ABITS-1:0] B1ADDR;
+ input [CFG_DBITS-1:0] B1DATA;
+ input [CFG_ENABLE_B-1:0] B1EN;
+
+ wire [13:0] A1ADDR_14;
+ wire [13:0] B1ADDR_14;
+ //wire [3:0] B1EN_4 = B1EN;
+
+ wire [1:0] DIP, DOP;
+ wire [15:0] DI, DO;
+
+ wire [15:0] DOBDO;
+ wire [1:0] DOPBDOP;
+
+ assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
+ assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
+
+ assign A1ADDR_14[13:CFG_ABITS] = 0;
+ assign A1ADDR_14[CFG_ABITS-1:0] = A1ADDR;
+ assign B1ADDR_14[13:CFG_ABITS] = 0;
+ assign B1ADDR_14[CFG_ABITS-1:0] = B1ADDR;
+
+ /*if (CFG_DBITS == 1) begin
+ assign WRITEDATAWIDTHB = 3'b000;
+ assign READDATAWIDTHA = 3'b000;
+ end else if (CFG_DBITS == 2) begin
+ assign WRITEDATAWIDTHB = 3'b001;
+ assign READDATAWIDTHA = 3'b001;
+ end else if (CFG_DBITS > 2 && CFG_DBITS <= 4) begin
+ assign WRITEDATAWIDTHB = 3'b010;
+ assign READDATAWIDTHA = 3'b010;
+ end else if (CFG_DBITS > 4 && CFG_DBITS <= 9) begin
+ assign WRITEDATAWIDTHB = 3'b011;
+ assign READDATAWIDTHA = 3'b011;
+ end else if (CFG_DBITS > 9 && CFG_DBITS <= 18) begin
+ //assign WRITEDATAWIDTHB = 3'b100;
+ assign READDATAWIDTHA = 3'b100;
+ end*/
+ generate if (CFG_DBITS > 8) begin
+ TDP_BRAM18 #(
+ //`include "brams_init_18.vh"
+ .READ_WIDTH_A(CFG_DBITS),
+ .READ_WIDTH_B(CFG_DBITS),
+ .WRITE_WIDTH_A(CFG_DBITS),
+ .WRITE_WIDTH_B(CFG_DBITS),
+ ) _TECHMAP_REPLACE_ (
+ .WRITEDATAA(16'hFFFF),
+ .WRITEDATAAP(2'b11),
+ .READDATAA(DO[15:0]),
+ .READDATAAP(DOP[2:0]),
+ .ADDRA(A1ADDR_14),
+ .CLOCKA(CLK2),
+ .READENABLEA(A1EN),
+ .WRITEENABLEA(1'b0),
+ .BYTEENABLEA(2'b0),
+ //.WRITEDATAWIDTHA(3'b0),
+ //.READDATAWIDTHA(READDATAWIDTHA),
+
+ .WRITEDATAB(DI),
+ .WRITEDATABP(DIP),
+ .READDATAB(DOBDO),
+ .READDATABP(DOPBDOP),
+ .ADDRB(B1ADDR_14),
+ .CLOCKB(CLK3),
+ .READENABLEB(1'b0),
+ .WRITEENABLEB(1'b1),
+ .BYTEENABLEB(B1EN)
+ //.WRITEDATAWIDTHB(WRITEDATAWIDTHB),
+ //.READDATAWIDTHB(3'b0)
+ );
+ end else begin
+ TDP_BRAM18 #(
+ //`include "brams_init_16.vh"
+ ) _TECHMAP_REPLACE_ (
+ .WRITEDATAA(16'hFFFF),
+ .WRITEDATAAP(2'b11),
+ .READDATAA(DO[15:0]),
+ .READDATAAP(DOP[2:0]),
+ .ADDRA(A1ADDR_14),
+ .CLOCKA(CLK2),
+ .READENABLEA(A1EN),
+ .WRITEENABLEA(1'b0),
+ .BYTEENABLEA(2'b0),
+ //.WRITEDATAWIDTHA(3'b0),
+ // .READDATAWIDTHA(READDATAWIDTHA),
+
+ .WRITEDATAB(DI),
+ .WRITEDATABP(DIP),
+ .READDATAB(DOBDO),
+ .READDATABP(DOPBDOP),
+ .ADDRB(B1ADDR_14),
+ .CLOCKB(CLK3),
+ .READENABLEB(1'b0),
+ .WRITEENABLEB(1'b1),
+ .BYTEENABLEB(B1EN)
+ //.WRITEDATAWIDTHB(WRITEDATAWIDTHB),
+ //.READDATAWIDTHB(3'b0)
+ );
+ end endgenerate
+endmodule
diff --git a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
new file mode 100644
index 0000000..25fb1e0
--- /dev/null
+++ b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
@@ -0,0 +1,882 @@
+// Copyright (C) 2020-2021 The SymbiFlow Authors.
+//
+// Use of this source code is governed by a ISC-style
+// license that can be found in the LICENSE file or at
+// https://opensource.org/licenses/ISC
+//
+// SPDX-License-Identifier:ISC
+
+(* abc9_flop, lib_whitebox *)
+module sh_dff(
+ output reg Q,
+ input D,
+ (* clkbuf_sink *)
+ input C
+);
+ parameter [0:0] INIT = 1'b0;
+ initial Q = INIT;
+
+ always @(posedge C)
+ Q <= D;
+endmodule
+
+module MUXCY(output O, input CI, DI, S);
+ assign O = S ? CI : DI;
+endmodule
+
+module XORCY(output O, input CI, LI);
+ assign O = CI ^ LI;
+endmodule
+
+(* abc9_box, lib_blackbox *)
+module adder_carry(
+ output sumout,
+ output cout,
+ input p,
+ input g,
+ input cin
+);
+ assign sumout = p ^ cin;
+ assign cout = p ? cin : g;
+
+endmodule
+
+(* abc9_box, lib_whitebox *)
+module adder_lut5(
+ output lut5_out,
+ (* abc9_carry *)
+ output cout,
+ input [0:4] in,
+ (* abc9_carry *)
+ input cin
+);
+ parameter [0:15] LUT=0;
+ parameter IN2_IS_CIN = 0;
+
+ wire [0:4] li = (IN2_IS_CIN) ? {in[0], in[1], cin, in[3], in[4]} : {in[0], in[1], in[2], in[3],in[4]};
+
+ // Output function
+ wire [0:15] s1 = li[0] ?
+ {LUT[0], LUT[2], LUT[4], LUT[6], LUT[8], LUT[10], LUT[12], LUT[14], LUT[16], LUT[18], LUT[20], LUT[22], LUT[24], LUT[26], LUT[28], LUT[30]}:
+ {LUT[1], LUT[3], LUT[5], LUT[7], LUT[9], LUT[11], LUT[13], LUT[15], LUT[17], LUT[19], LUT[21], LUT[23], LUT[25], LUT[27], LUT[29], LUT[31]};
+
+ wire [0:7] s2 = li[1] ? {s1[0], s1[2], s1[4], s1[6], s1[8], s1[10], s1[12], s1[14]} :
+ {s1[1], s1[3], s1[5], s1[7], s1[9], s1[11], s1[13], s1[15]};
+
+ wire [0:3] s3 = li[2] ? {s2[0], s2[2], s2[4], s2[6]} : {s2[1], s2[3], s2[5], s2[7]};
+ wire [0:1] s4 = li[3] ? {s3[0], s3[2]} : {s3[1], s3[3]};
+
+ assign lut5_out = li[4] ? s4[0] : s4[1];
+
+ // Carry out function
+ assign cout = (s3[2]) ? cin : s3[3];
+
+endmodule
+
+
+
+(* abc9_lut=1, lib_whitebox *)
+module frac_lut6(
+ input [0:5] in,
+ output [0:3] lut4_out,
+ output [0:1] lut5_out,
+ output lut6_out
+);
+ parameter [0:63] LUT = 0;
+ // Effective LUT input
+ wire [0:5] li = in;
+
+ // Output function
+ wire [0:31] s1 = li[0] ?
+ {LUT[0] , LUT[2] , LUT[4] , LUT[6] , LUT[8] , LUT[10], LUT[12], LUT[14],
+ LUT[16], LUT[18], LUT[20], LUT[22], LUT[24], LUT[26], LUT[28], LUT[30],
+ LUT[32], LUT[34], LUT[36], LUT[38], LUT[40], LUT[42], LUT[44], LUT[46],
+ LUT[48], LUT[50], LUT[52], LUT[54], LUT[56], LUT[58], LUT[60], LUT[62]}:
+ {LUT[1] , LUT[3] , LUT[5] , LUT[7] , LUT[9] , LUT[11], LUT[13], LUT[15],
+ LUT[17], LUT[19], LUT[21], LUT[23], LUT[25], LUT[27], LUT[29], LUT[31],
+ LUT[33], LUT[35], LUT[37], LUT[39], LUT[41], LUT[43], LUT[45], LUT[47],
+ LUT[49], LUT[51], LUT[53], LUT[55], LUT[57], LUT[59], LUT[61], LUT[63]};
+
+ wire [0:15] s2 = li[1] ?
+ {s1[0] , s1[2] , s1[4] , s1[6] , s1[8] , s1[10], s1[12], s1[14],
+ s1[16], s1[18], s1[20], s1[22], s1[24], s1[26], s1[28], s1[30]}:
+ {s1[1] , s1[3] , s1[5] , s1[7] , s1[9] , s1[11], s1[13], s1[15],
+ s1[17], s1[19], s1[21], s1[23], s1[25], s1[27], s1[29], s1[31]};
+
+ wire [0:7] s3 = li[2] ?
+ {s2[0], s2[2], s2[4], s2[6], s2[8], s2[10], s2[12], s2[14]}:
+ {s2[1], s2[3], s2[5], s2[7], s2[9], s2[11], s2[13], s2[15]};
+
+ wire [0:3] s4 = li[3] ? {s3[0], s3[2], s3[4], s3[6]}:
+ {s3[1], s3[3], s3[5], s3[7]};
+
+ wire [0:1] s5 = li[4] ? {s4[0], s4[2]} : {s4[1], s4[3]};
+
+ assign lut4_out[0] = s4[0];
+ assign lut4_out[1] = s4[1];
+ assign lut4_out[2] = s4[2];
+ assign lut4_out[3] = s4[3];
+
+ assign lut5_out[0] = s0[0];
+ assign lut5_out[1] = s5[1];
+
+ assign lut6_out = li[5] ? s5[0] : s5[1];
+
+endmodule
+
+(* abc9_flop, lib_whitebox *)
+module dff(
+ output reg Q,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C
+);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ initial Q = INIT;
+ case(|IS_C_INVERTED)
+ 1'b0:
+ always @(posedge C)
+ Q <= D;
+ 1'b1:
+ always @(negedge C)
+ Q <= D;
+ endcase
+endmodule
+
+(* abc9_flop, lib_whitebox *)
+module dffr(
+ output reg Q,
+ input D,
+ input R,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C
+);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ initial Q = INIT;
+ case(|IS_C_INVERTED)
+ 1'b0:
+ always @(posedge C or posedge R)
+ if (R)
+ Q <= 1'b0;
+ else
+ Q <= D;
+ 1'b1:
+ always @(negedge C or posedge R)
+ if (R)
+ Q <= 1'b0;
+ else
+ Q <= D;
+ endcase
+endmodule
+
+(* abc9_flop, lib_whitebox *)
+module dffre(
+ output reg Q,
+ input D,
+ input R,
+ input E,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C
+);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ initial Q = INIT;
+ case(|IS_C_INVERTED)
+ 1'b0:
+ always @(posedge C or posedge R)
+ if (R)
+ Q <= 1'b0;
+ else if(E)
+ Q <= D;
+ 1'b1:
+ always @(negedge C or posedge R)
+ if (R)
+ Q <= 1'b0;
+ else if(E)
+ Q <= D;
+ endcase
+endmodule
+
+module dffs(
+ output reg Q,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C,
+ input S
+);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ initial Q = INIT;
+ case(|IS_C_INVERTED)
+ 1'b0:
+ always @(posedge C or negedge S)
+ if (S)
+ Q <= 1'b1;
+ else
+ Q <= D;
+ 1'b1:
+ always @(negedge C or negedge S)
+ if (S)
+ Q <= 1'b1;
+ else
+ Q <= D;
+ endcase
+endmodule
+
+module dffse(
+ output reg Q,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C,
+ input S,
+ input E,
+);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ initial Q = INIT;
+ case(|IS_C_INVERTED)
+ 1'b0:
+ always @(posedge C or negedge S)
+ if (S)
+ Q <= 1'b1;
+ else if(E)
+ Q <= D;
+ 1'b1:
+ always @(negedge C or negedge S)
+ if (S)
+ Q <= 1'b1;
+ else if(E)
+ Q <= D;
+ endcase
+endmodule
+
+module dffsr(
+ output reg Q,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C,
+ input R,
+ input S
+);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ initial Q = INIT;
+ case(|IS_C_INVERTED)
+ 1'b0:
+ always @(posedge C or negedge S or negedge R)
+ if (S)
+ Q <= 1'b1;
+ else if (R)
+ Q <= 1'b0;
+ else
+ Q <= D;
+ 1'b1:
+ always @(negedge C or negedge S or negedge R)
+ if (S)
+ Q <= 1'b1;
+ else if (R)
+ Q <= 1'b0;
+ else
+ Q <= D;
+ endcase
+endmodule
+
+/*
+module dffsre(
+ output reg Q,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_C_INVERTED" *)
+ input C,
+ input E,
+ input R,
+ input S
+);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ initial Q = INIT;
+ case(|IS_C_INVERTED)
+ 1'b0:
+ always @(posedge C or posedge S or posedge R)
+ if (S)
+ Q <= 1'b1;
+ else if (R)
+ Q <= 1'b0;
+ else if (E)
+ Q <= D;
+ endcase
+endmodule
+*/
+
+module dffsre(
+ output reg Q,
+ input D,
+ (* clkbuf_sink *)
+ input C,
+ input E,
+ input R,
+ input S
+);
+ parameter [0:0] INIT = 1'b0;
+ initial Q = INIT;
+
+ always @(posedge C or negedge S or negedge R)
+ if (!R)
+ Q <= 1'b0;
+ else if (!S)
+ Q <= 1'b1;
+ else if (E)
+ Q <= D;
+
+endmodule
+
+module dffnsre(
+ output reg Q,
+ input D,
+ (* clkbuf_sink *)
+ input C,
+ input E,
+ input R,
+ input S
+);
+ parameter [0:0] INIT = 1'b0;
+ initial Q = INIT;
+
+ always @(negedge C or negedge S or negedge R)
+ if (!R)
+ Q <= 1'b0;
+ else if (!S)
+ Q <= 1'b1;
+ else if (E)
+ Q <= D;
+
+endmodule
+
+/*
+(* abc9_flop, lib_whitebox *)
+module latchsre (
+ output reg Q,
+ input S,
+ input R,
+ input D,
+ input G,
+ input E
+);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ initial Q = INIT;
+ always @*
+ begin
+ if (R) Q <= 1'b0;
+ if (S) Q <= 1'b1;
+ else if (E && G) Q <= D;
+ end
+endmodule
+*/
+
+(* abc9_flop, lib_whitebox *)
+module latchsre (
+ output reg Q,
+ input S,
+ input R,
+ input D,
+ input G,
+ input E
+);
+ parameter [0:0] INIT = 1'b0;
+ initial Q = INIT;
+ always @*
+ begin
+ if (!R)
+ Q <= 1'b0;
+ else if (!S)
+ Q <= 1'b1;
+ else if (E && G)
+ Q <= D;
+ end
+endmodule
+
+(* abc9_flop, lib_whitebox *)
+module latchnsre (
+ output reg Q,
+ input S,
+ input R,
+ input D,
+ input G,
+ input E
+);
+ parameter [0:0] INIT = 1'b0;
+ initial Q = INIT;
+ always @*
+ begin
+ if (!R)
+ Q <= 1'b0;
+ else if (!S)
+ Q <= 1'b1;
+ else if (E && !G)
+ Q <= D;
+ end
+endmodule
+
+(* abc9_flop, lib_whitebox *)
+module scff(
+ output reg Q,
+ input D,
+ input clk
+);
+ parameter [0:0] INIT = 1'b0;
+ initial Q = INIT;
+
+ always @(posedge clk)
+ Q <= D;
+endmodule
+
+module DP_RAM16K (
+ input rclk,
+ input wclk,
+ input wen,
+ input ren,
+ input[8:0] waddr,
+ input[8:0] raddr,
+ input[31:0] d_in,
+ input[31:0] wenb,
+ output[31:0] d_out );
+
+ _dual_port_sram memory_0 (
+ .wclk (wclk),
+ .wen (wen),
+ .waddr (waddr),
+ .data_in (d_in),
+ .rclk (rclk),
+ .ren (ren),
+ .raddr (raddr),
+ .wenb (wenb),
+ .d_out (d_out) );
+
+endmodule
+
+module _dual_port_sram (
+ input wclk,
+ input wen,
+ input[8:0] waddr,
+ input[31:0] data_in,
+ input rclk,
+ input ren,
+ input[8:0] raddr,
+ input[31:0] wenb,
+ output[31:0] d_out );
+
+ // MODE 0: 512 x 32
+ // MODE 1: 1024 x 16
+ // MODE 2: 1024 x 8
+ // MODE 3: 2048 x 4
+
+ integer i;
+ reg[31:0] ram[512:0];
+ reg[31:0] internal;
+ // The memory is self initialised
+
+ initial begin
+ for (i=0;i<=512;i=i+1)
+ begin
+ ram[i] = 0;
+ end
+ internal = 31'b0;
+ end
+
+ wire [31:0] WMASK;
+
+ assign d_out = internal;
+ assign WMASK = wenb;
+
+ always @(posedge wclk) begin
+ if(!wen) begin
+ if (WMASK[ 0]) ram[waddr][ 0] <= data_in[ 0];
+ if (WMASK[ 1]) ram[waddr][ 1] <= data_in[ 1];
+ if (WMASK[ 2]) ram[waddr][ 2] <= data_in[ 2];
+ if (WMASK[ 3]) ram[waddr][ 3] <= data_in[ 3];
+ if (WMASK[ 4]) ram[waddr][ 4] <= data_in[ 4];
+ if (WMASK[ 5]) ram[waddr][ 5] <= data_in[ 5];
+ if (WMASK[ 6]) ram[waddr][ 6] <= data_in[ 6];
+ if (WMASK[ 7]) ram[waddr][ 7] <= data_in[ 7];
+ if (WMASK[ 8]) ram[waddr][ 8] <= data_in[ 8];
+ if (WMASK[ 9]) ram[waddr][ 9] <= data_in[ 9];
+ if (WMASK[10]) ram[waddr][10] <= data_in[10];
+ if (WMASK[11]) ram[waddr][11] <= data_in[11];
+ if (WMASK[12]) ram[waddr][12] <= data_in[12];
+ if (WMASK[13]) ram[waddr][13] <= data_in[13];
+ if (WMASK[14]) ram[waddr][14] <= data_in[14];
+ if (WMASK[15]) ram[waddr][15] <= data_in[15];
+ if (WMASK[16]) ram[waddr][16] <= data_in[16];
+ if (WMASK[17]) ram[waddr][17] <= data_in[17];
+ if (WMASK[18]) ram[waddr][18] <= data_in[18];
+ if (WMASK[19]) ram[waddr][19] <= data_in[19];
+ if (WMASK[20]) ram[waddr][20] <= data_in[20];
+ if (WMASK[21]) ram[waddr][21] <= data_in[21];
+ if (WMASK[22]) ram[waddr][22] <= data_in[22];
+ if (WMASK[23]) ram[waddr][23] <= data_in[23];
+ if (WMASK[24]) ram[waddr][24] <= data_in[24];
+ if (WMASK[25]) ram[waddr][25] <= data_in[25];
+ if (WMASK[26]) ram[waddr][26] <= data_in[26];
+ if (WMASK[27]) ram[waddr][27] <= data_in[27];
+ if (WMASK[28]) ram[waddr][28] <= data_in[28];
+ if (WMASK[29]) ram[waddr][29] <= data_in[29];
+ if (WMASK[30]) ram[waddr][30] <= data_in[30];
+ if (WMASK[31]) ram[waddr][31] <= data_in[31];
+ end
+ end
+
+ always @(posedge rclk) begin
+ if(!ren) begin
+ internal <= ram[raddr];
+ end
+ end
+endmodule
+
+module QL_DSP (
+ input CLK,
+ input [15:0] A, B, C, D,
+ output [31:0] O,
+ output CO // Currently unused, left in case we want to support signed operations in the future.
+);
+ parameter [0:0] A_REG = 0;
+ parameter [0:0] B_REG = 0;
+ parameter [0:0] C_REG = 0;
+ parameter [0:0] D_REG = 0;
+ parameter [0:0] ENABLE_DSP = 0;
+ parameter [0:0] A_SIGNED = 0;
+ parameter [0:0] B_SIGNED = 0;
+
+ wire [15:0] iA, iB, iC, iD;
+ wire [15:0] iF, iJ, iK, iG;
+
+ // Regs C and A, currently unused
+ reg [15:0] rC, rA;
+
+ assign iC = C_REG ? rC : C;
+ assign iA = A_REG ? rA : A;
+
+ // Regs B and D, currently unused
+ reg [15:0] rB, rD;
+
+ assign iB = B_REG ? rB : B;
+ assign iD = D_REG ? rD : D;
+
+ // Multiplier Stage
+ wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
+ wire [15:0] Ah, Al, Bh, Bl;
+ assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
+ assign Al = {8'b0, iA[ 7: 0]};
+ assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
+ assign Bl = {8'b0, iB[ 7: 0]};
+ assign p_Ah_Bh = Ah * Bh; // F
+ assign p_Al_Bh = {8'b0, Al[7:0]} * Bh; // J
+ assign p_Ah_Bl = Ah * {8'b0, Bl[7:0]}; // K
+ assign p_Al_Bl = Al * Bl; // G
+
+ assign iF = p_Ah_Bh;
+ assign iJ = p_Al_Bh;
+
+ assign iK = p_Ah_Bl;
+ assign iG = p_Al_Bl;
+
+ // Adder Stage
+ wire [23:0] iK_e = {A_SIGNED ? {8{iK[15]}} : 8'b0, iK};
+ wire [23:0] iJ_e = {B_SIGNED ? {8{iJ[15]}} : 8'b0, iJ};
+ assign iL = iG + (iK_e << 8) + (iJ_e << 8) + (iF << 16);
+
+ // Output Stage
+ assign O = iL;
+
+endmodule
+
+
+module TDP_BRAM18 (
+ (* clkbuf_sink *)
+ input CLOCKA,
+ (* clkbuf_sink *)
+ input CLOCKB,
+ input READENABLEA,
+ input READENABLEB,
+ input [13:0] ADDRA,
+ input [13:0] ADDRB,
+ input [15:0] WRITEDATAA,
+ input [15:0] WRITEDATAB,
+ input [1:0] WRITEDATAAP,
+ input [1:0] WRITEDATABP,
+ input WRITEENABLEA,
+ input WRITEENABLEB,
+ input [1:0] BYTEENABLEA,
+ input [1:0] BYTEENABLEB,
+ //input [2:0] WRITEDATAWIDTHA,
+ //input [2:0] WRITEDATAWIDTHB,
+ //input [2:0] READDATAWIDTHA,
+ //input [2:0] READDATAWIDTHB,
+ output [15:0] READDATAA,
+ output [15:0] READDATAB,
+ output [1:0] READDATAAP,
+ output [1:0] READDATABP
+);
+ parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter integer READ_WIDTH_A = 0;
+ parameter integer READ_WIDTH_B = 0;
+ parameter integer WRITE_WIDTH_A = 0;
+ parameter integer WRITE_WIDTH_B = 0;
+
+endmodule
+
+module TDP_BRAM36 (
+ (* clkbuf_sink *)
+ input CLOCKA,
+ (* clkbuf_sink *)
+ input CLOCKB,
+ input READENABLEA,
+ input READENABLEB,
+ input [14:0] ADDRA,
+ input [14:0] ADDRB,
+ input [31:0] WRITEDATAA,
+ input [31:0] WRITEDATAB,
+ input [3:0] WRITEDATAAP,
+ input [3:0] WRITEDATABP,
+ input WRITEENABLEA,
+ input WRITEENABLEB,
+ input [3:0] BYTEENABLEA,
+ input [3:0] BYTEENABLEB,
+ //input [2:0] WRITEDATAWIDTHA,
+ //input [2:0] WRITEDATAWIDTHB,
+ //input [2:0] READDATAWIDTHA,
+ //input [2:0] READDATAWIDTHB,
+ output [31:0] READDATAA,
+ output [31:0] READDATAB,
+ output [3:0] READDATAAP,
+ output [3:0] READDATABP
+);
+ parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ parameter integer READ_WIDTH_A = 0;
+ parameter integer READ_WIDTH_B = 0;
+ parameter integer WRITE_WIDTH_A = 0;
+ parameter integer WRITE_WIDTH_B = 0;
+
+endmodule
diff --git a/ql-qlf-plugin/qlf_k6n10f/dsp_map.v b/ql-qlf-plugin/qlf_k6n10f/dsp_map.v
new file mode 100644
index 0000000..4b8ae64
--- /dev/null
+++ b/ql-qlf-plugin/qlf_k6n10f/dsp_map.v
@@ -0,0 +1,27 @@
+// Copyright (C) 2020-2021 The SymbiFlow Authors.
+//
+// Use of this source code is governed by a ISC-style
+// license that can be found in the LICENSE file or at
+// https://opensource.org/licenses/ISC
+//
+// SPDX-License-Identifier:ISC
+
+module \$__MUL16X16 (input [15:0] A, input [15:0] B, output [31:0] Y);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 0;
+ parameter B_WIDTH = 0;
+ parameter Y_WIDTH = 0;
+
+ QL_DSP #(
+ .A_REG(1'b0),
+ .B_REG(1'b0),
+ .C_REG(1'b0),
+ .D_REG(1'b0),
+ .ENABLE_DSP(1'b1),
+ ) _TECHMAP_REPLACE_ (
+ .A(A),
+ .B(B),
+ .O(Y),
+ );
+endmodule
diff --git a/ql-qlf-plugin/qlf_k6n10f/ffs_map.v b/ql-qlf-plugin/qlf_k6n10f/ffs_map.v
new file mode 100644
index 0000000..3c5e9f0
--- /dev/null
+++ b/ql-qlf-plugin/qlf_k6n10f/ffs_map.v
@@ -0,0 +1,197 @@
+// Copyright (C) 2020-2021 The SymbiFlow Authors.
+//
+// Use of this source code is governed by a ISC-style
+// license that can be found in the LICENSE file or at
+// https://opensource.org/licenses/ISC
+//
+// SPDX-License-Identifier:ISC
+
+// Basic DFF
+
+module \$_DFF_P_ (D, C, Q);
+ input D;
+ input C;
+ output Q;
+ dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(1'b1), .S(1'b1));
+endmodule
+
+// Async reset
+module \$_DFF_PP0_ (D, C, R, Q);
+ input D;
+ input C;
+ input R;
+ output Q;
+ dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(!R), .S(1'b1));
+endmodule
+
+// Async set
+module \$_DFF_PP1_ (D, C, R, Q);
+ input D;
+ input C;
+ input R;
+ output Q;
+ dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(1'b1), .S(!R));
+endmodule
+
+// Async reset, enable
+
+module \$_DFFE_PP0P_ (D, C, E, R, Q);
+ input D;
+ input C;
+ input E;
+ input R;
+ output Q;
+ dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(!R), .S(1'b1));
+endmodule
+
+// Async set, enable
+
+module \$_DFFE_PP1P_ (D, C, E, R, Q);
+ input D;
+ input C;
+ input E;
+ input R;
+ output Q;
+ dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(!R));
+endmodule
+
+// Async set & reset
+
+module \$_DFFSR_PPP_ (D, C, R, S, Q);
+ input D;
+ input C;
+ input R;
+ input S;
+ output Q;
+ dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(!R), .S(!S));
+endmodule
+
+// Async set, reset & enable
+
+module \$_DFFSRE_PPPP_ (D, Q, C, E, R, S);
+ input D;
+ input C;
+ input E;
+ input R;
+ input S;
+ output Q;
+ dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(!R), .S(!S));
+endmodule
+
+// Latch with async set and reset
+module \$_DLATCHSR_PPP_ (input E, S, R, D, output Q);
+ latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S));
+endmodule
+
+module \$_DLATCHSR_NPP_ (input E, S, R, D, output Q);
+ latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S));
+endmodule
+
+// The following techmap operation are not performed right now
+// as Negative edge FF are not legalized in synth_quicklogic for qlf_k6n10
+// but in case we implement clock inversion in the future, the support is ready for it.
+
+module \$_DFF_N_ (D, C, Q);
+ input D;
+ input C;
+ output Q;
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(1'b1), .S(1'b1));
+endmodule
+
+module \$_DFF_NP0_ (D, C, R, Q);
+ input D;
+ input C;
+ input R;
+ output Q;
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(!R), .S(1'b1));
+endmodule
+
+module \$_DFF_NP1_ (D, C, R, Q);
+ input D;
+ input C;
+ input R;
+ output Q;
+ dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(1'b1), .S(!R));
+endmodule
+
+module \$_DFFE_NP0P_ (D, C, E, R, Q);
+ input D;
+ input C;
+ input E;
+ input R;
+ output Q;
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(!R), .S(1'b1));
+endmodule
+
+module \$_DFFE_NP1P_ (D, C, E, R, Q);
+ input D;
+ input C;
+ input E;
+ input R;
+ output Q;
+ parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
+ dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(!R));
+endmodule
+
+module \$_DFFSR_NPP_ (D, C, R, S, Q);
+ input D;
+ input C;
+ input R;
+ input S;
+ output Q;
+ dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(1'b1), .R(!R), .S(!S));
+endmodule
+
+module \$_DFFSRE_PPPP_ (D, C, E, R, S, Q);
+ input D;
+ input C;
+ input E;
+ input R;
+ input S;
+ output Q;
+ dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(!R), .S(!S));
+endmodule
+
+module \$__SHREG_DFF_P_ (D, Q, C);
+ input D;
+ input C;
+ output Q;
+
+ parameter DEPTH = 2;
+ reg [DEPTH-2:0] q;
+ genvar i;
+ generate for (i = 0; i < DEPTH; i = i + 1) begin: slice
+
+
+ // First in chain
+ generate if (i == 0) begin
+ sh_dff #() shreg_beg (
+ .Q(q[i]),
+ .D(D),
+ .C(C)
+ );
+ end endgenerate
+ // Middle in chain
+ generate if (i > 0 && i != DEPTH-1) begin
+ sh_dff #() shreg_mid (
+ .Q(q[i]),
+ .D(q[i-1]),
+ .C(C)
+ );
+ end endgenerate
+ // Last in chain
+ generate if (i == DEPTH-1) begin
+ sh_dff #() shreg_end (
+ .Q(Q),
+ .D(q[i-1]),
+ .C(C)
+ );
+ end endgenerate
+ end: slice
+ endgenerate
+
+endmodule
+
diff --git a/ql-qlf-plugin/qlf_k6n10f/lut_map.v b/ql-qlf-plugin/qlf_k6n10f/lut_map.v
new file mode 100644
index 0000000..5d8c421
--- /dev/null
+++ b/ql-qlf-plugin/qlf_k6n10f/lut_map.v
@@ -0,0 +1,31 @@
+// Copyright (C) 2020-2021 The SymbiFlow Authors.
+//
+// Use of this source code is governed by a ISC-style
+// license that can be found in the LICENSE file or at
+// https://opensource.org/licenses/ISC
+//
+// SPDX-License-Identifier:ISC
+
+`ifndef NO_LUT
+module \$lut (A, Y);
+ parameter WIDTH = 0;
+ parameter LUT = 0;
+
+ (* force_downto *)
+ input [WIDTH-1:0] A;
+ output Y;
+
+/* generate
+ if (WIDTH == 6) begin
+ frac_lut6 #(.LUT(LUT)) _TECHMAP_REPLACE_ (.lut6_out(Y),.in(A));
+
+ end else begin
+ wire _TECHMAP_FAIL_ = 1;
+ end
+ endgenerate */
+
+endmodule
+`endif
+
+
+
diff --git a/ql-qlf-plugin/synth_quicklogic.cc b/ql-qlf-plugin/synth_quicklogic.cc
index 241005d..62419f7 100644
--- a/ql-qlf-plugin/synth_quicklogic.cc
+++ b/ql-qlf-plugin/synth_quicklogic.cc
@@ -44,6 +44,7 @@
log(" - pp3 : pp3 \n");
log(" - qlf_k4n8 : qlf_k4n8 \n");
log(" - qlf_k6n10: qlf_k6n10 \n");
+ log(" - qlf_k6n10f: qlf_k6n10f \n");
log("\n");
log(" -no_abc_opt\n");
log(" By default most of ABC logic optimization features is\n");
@@ -166,7 +167,7 @@
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
- if (family != "pp3" && family != "qlf_k4n8" && family != "qlf_k6n10")
+ if (family != "pp3" && family != "qlf_k4n8" && family != "qlf_k6n10" && family != "qlf_k6n10f")
log_cmd_error("Invalid family specified: '%s'\n", family.c_str());
if (family != "pp3") {
@@ -247,7 +248,7 @@
run("opt_clean");
}
- if (check_label("map_bram", "(skip if -no_bram)") && (family == "qlf_k6n10" || family == "pp3") && inferBram) {
+ if (check_label("map_bram", "(skip if -no_bram)") && (family == "qlf_k6n10" || family == "qlf_k6n10f" || family == "pp3") && inferBram) {
run("memory_bram -rules +/quicklogic/" + family + "/brams.txt");
if (family == "pp3") {
run("pp3_braminit");
@@ -264,7 +265,7 @@
}
if (check_label("map_gates")) {
- if (inferAdder && (family == "qlf_k4n8" || family == "qlf_k6n10")) {
+ if (inferAdder && (family == "qlf_k4n8" || family == "qlf_k6n10" || family == "qlf_k6n10f")) {
run("techmap -map +/techmap.v -map +/quicklogic/" + family + "/arith_map.v");
} else {
run("techmap");
@@ -284,7 +285,7 @@
if (family == "qlf_k4n8") {
run("shregmap -minlen 8 -maxlen 8");
run("dfflegalize -cell $_DFF_P_ 0 -cell $_DFF_P??_ 0 -cell $_DFF_N_ 0 -cell $_DFF_N??_ 0 -cell $_DFFSR_???_ 0");
- } else if (family == "qlf_k6n10") {
+ } else if (family == "qlf_k6n10" || family == "qlf_k6n10f") {
run("dfflegalize -cell $_DFF_P_ 0 -cell $_DFF_PP?_ 0 -cell $_DFFE_PP?P_ 0 -cell $_DFFSR_PPP_ 0 -cell $_DFFSRE_PPPP_ 0 -cell "
"$_DLATCHSR_PPP_ 0");
// In case we add clock inversion in the future.
@@ -308,7 +309,7 @@
if (check_label("map_luts")) {
if (abcOpt) {
- if (family == "qlf_k6n10") {
+ if (family == "qlf_k6n10" || family == "qlf_k6n10f") {
run("abc -lut 6 ");
} else if (family == "qlf_k4n8") {
run("abc -lut 4 ");
@@ -337,7 +338,7 @@
run("opt_lut");
}
- if (check_label("map_cells") && (family == "qlf_k6n10" || family == "pp3")) {
+ if (check_label("map_cells") && (family == "qlf_k6n10" || family == "pp3" || family == "qlf_k6n10f")) {
std::string techMapArgs;
techMapArgs = "-map +/quicklogic/" + family + "/lut_map.v";
run("techmap " + techMapArgs);
