SDC: Add test for SDC written for design restored from json
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
diff --git a/sdc-plugin/tests/Makefile b/sdc-plugin/tests/Makefile
index 3b45b57..c507ee8 100644
--- a/sdc-plugin/tests/Makefile
+++ b/sdc-plugin/tests/Makefile
@@ -11,7 +11,8 @@
pll_approx_equal \
set_false_path \
set_max_delay \
- set_clock_groups
+ set_clock_groups \
+ restore_from_json
include $(shell pwd)/../../Makefile_test.common
@@ -24,3 +25,4 @@
set_false_path_verify = $(call diff_test,set_false_path,sdc)
set_max_delay_verify = $(call diff_test,set_max_delay,sdc)
set_clock_groups_verify = $(call diff_test,set_clock_groups,sdc)
+restore_from_json_verify = diff restore_from_json/restore_from_json_1.sdc restore_from_json/restore_from_json_2.sdc
diff --git a/sdc-plugin/tests/restore_from_json/restore_from_json.tcl b/sdc-plugin/tests/restore_from_json/restore_from_json.tcl
new file mode 100644
index 0000000..288419b
--- /dev/null
+++ b/sdc-plugin/tests/restore_from_json/restore_from_json.tcl
@@ -0,0 +1,16 @@
+yosys -import
+
+plugin -i sdc
+
+yosys -import
+
+read_verilog $::env(DESIGN_TOP).v
+synth_xilinx
+create_clock -period 10 clk
+propagate_clocks
+write_sdc $::env(DESIGN_TOP)_1.sdc
+write_json $::env(DESIGN_TOP).json
+
+design -push
+read_json $::env(DESIGN_TOP).json
+write_sdc $::env(DESIGN_TOP)_2.sdc
diff --git a/sdc-plugin/tests/restore_from_json/restore_from_json.v b/sdc-plugin/tests/restore_from_json/restore_from_json.v
new file mode 100644
index 0000000..0c35ede
--- /dev/null
+++ b/sdc-plugin/tests/restore_from_json/restore_from_json.v
@@ -0,0 +1,11 @@
+module top(input clk, input i, output o);
+
+reg [0:0] outff = 0;
+
+assign o = outff;
+
+always @(posedge clk) begin
+ outff <= i;
+end
+
+endmodule
