Merge pull request #41 from antmicro/set_max_delay
SDC: Add set_max_delay command
diff --git a/sdc-plugin/Makefile b/sdc-plugin/Makefile
index b4694ca..0c9461d 100644
--- a/sdc-plugin/Makefile
+++ b/sdc-plugin/Makefile
@@ -4,7 +4,7 @@
LDLIBS = $(shell yosys-config --ldlibs)
PLUGINS_DIR = $(shell yosys-config --datdir)/plugins
-OBJS = buffers.o clocks.o propagation.o sdc.o
+OBJS = buffers.o clocks.o propagation.o sdc.o sdc_writer.o set_false_path.o set_max_delay.o
sdc.so: $(OBJS)
$(CXX) $(CXXFLAGS) $(LDFLAGS) -shared -o $@ $^ $(LDLIBS)
diff --git a/sdc-plugin/clocks.h b/sdc-plugin/clocks.h
index ff02bd5..f5b491c 100644
--- a/sdc-plugin/clocks.h
+++ b/sdc-plugin/clocks.h
@@ -71,6 +71,9 @@
void Propagate(BufferPropagation* pass);
void Propagate(ClockDividerPropagation* pass);
void WriteSdc(std::ostream& file);
+ const std::vector<Clock> GetClocks() {
+ return clocks_;
+ }
private:
std::vector<Clock> clocks_;
diff --git a/sdc-plugin/sdc.cc b/sdc-plugin/sdc.cc
index 4233d01..df09526 100644
--- a/sdc-plugin/sdc.cc
+++ b/sdc-plugin/sdc.cc
@@ -21,6 +21,9 @@
#include "kernel/register.h"
#include "kernel/rtlil.h"
#include "propagation.h"
+#include "set_false_path.h"
+#include "set_max_delay.h"
+#include "sdc_writer.h"
USING_YOSYS_NAMESPACE
@@ -57,8 +60,8 @@
};
struct WriteSdcCmd : public Backend {
- WriteSdcCmd(Clocks& clocks)
- : Backend("sdc", "Write SDC file"), clocks_(clocks) {}
+ WriteSdcCmd(Clocks& clocks, SdcWriter& sdc_writer)
+ : Backend("sdc", "Write SDC file"), clocks_(clocks), sdc_writer_(sdc_writer) {}
void help() override {
log("\n");
@@ -75,10 +78,11 @@
}
log("\nWriting out clock constraints file(SDC)\n");
extra_args(f, filename, args, 1);
- clocks_.WriteSdc(*f);
+ sdc_writer_.WriteSdc(clocks_, *f);
}
Clocks& clocks_;
+ SdcWriter& sdc_writer_;
};
struct CreateClockCmd : public Pass {
@@ -246,10 +250,12 @@
class SdcPlugin {
public:
SdcPlugin()
- : write_sdc_cmd_(clocks_),
+ : write_sdc_cmd_(clocks_, sdc_writer_),
create_clock_cmd_(clocks_),
get_clocks_cmd_(clocks_),
- propagate_clocks_cmd_(clocks_) {
+ propagate_clocks_cmd_(clocks_),
+ set_false_path_cmd_(sdc_writer_),
+ set_max_delay_cmd_(sdc_writer_) {
log("Loaded SDC plugin\n");
}
@@ -258,9 +264,12 @@
CreateClockCmd create_clock_cmd_;
GetClocksCmd get_clocks_cmd_;
PropagateClocksCmd propagate_clocks_cmd_;
+ SetFalsePath set_false_path_cmd_;
+ SetMaxDelay set_max_delay_cmd_;
private:
Clocks clocks_;
+ SdcWriter sdc_writer_;
} SdcPlugin;
PRIVATE_NAMESPACE_END
diff --git a/sdc-plugin/sdc_writer.cc b/sdc-plugin/sdc_writer.cc
new file mode 100644
index 0000000..3c106d3
--- /dev/null
+++ b/sdc-plugin/sdc_writer.cc
@@ -0,0 +1,81 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2020 The Symbiflow Authors
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "sdc_writer.h"
+
+USING_YOSYS_NAMESPACE
+
+void SdcWriter::AddFalsePath(FalsePath false_path) {
+ false_paths_.push_back(false_path);
+}
+
+void SdcWriter::SetMaxDelay(TimingPath timing_path) {
+ timing_paths_.push_back(timing_path);
+}
+
+void SdcWriter::WriteSdc(Clocks& clocks, std::ostream& file) {
+ WriteClocks(clocks, file);
+ WriteFalsePaths(file);
+ WriteMaxDelay(file);
+}
+
+void SdcWriter::WriteClocks(Clocks& clocks, std::ostream& file) {
+ for (auto clock : clocks.GetClocks()) {
+ auto clock_wires = clock.GetClockWires();
+ // FIXME: Input port nets are not found in VPR
+ if (std::all_of(clock_wires.begin(), clock_wires.end(),
+ [&](RTLIL::Wire* wire) { return wire->port_input; })) {
+ continue;
+ }
+ file << "create_clock -period " << clock.Period();
+ file << " -waveform {" << clock.RisingEdge() << " "
+ << clock.FallingEdge() << "}";
+ for (auto clock_wire : clock_wires) {
+ if (clock_wire->port_input) {
+ continue;
+ }
+ file << " " << Clock::ClockWireName(clock_wire);
+ }
+ file << std::endl;
+ }
+}
+
+void SdcWriter::WriteFalsePaths(std::ostream& file) {
+ for (auto path : false_paths_) {
+ file << "set_false_path";
+ if (!path.from_pin.empty()) {
+ file << " -from " << path.from_pin;
+ }
+ if (!path.to_pin.empty()) {
+ file << " -to " << path.to_pin;
+ }
+ file << std::endl;
+ }
+}
+
+void SdcWriter::WriteMaxDelay(std::ostream& file) {
+ for (auto path : timing_paths_) {
+ file << "set_max_delay " << path.max_delay;
+ if (!path.from_pin.empty()) {
+ file << " -from " << path.from_pin;
+ }
+ if (!path.to_pin.empty()) {
+ file << " -to " << path.to_pin;
+ }
+ file << std::endl;
+ }
+}
diff --git a/sdc-plugin/sdc_writer.h b/sdc-plugin/sdc_writer.h
new file mode 100644
index 0000000..5620841
--- /dev/null
+++ b/sdc-plugin/sdc_writer.h
@@ -0,0 +1,50 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2020 The Symbiflow Authors
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef _SDC_WRITER_H_
+#define _SDC_WRITER_H_
+#include "clocks.h"
+
+USING_YOSYS_NAMESPACE
+
+struct FalsePath {
+ std::string from_pin;
+ std::string to_pin;
+};
+
+struct TimingPath {
+ std::string from_pin;
+ std::string to_pin;
+ float max_delay;
+};
+
+class SdcWriter {
+ public:
+ void AddFalsePath(FalsePath false_path);
+ void SetMaxDelay(TimingPath timing_path);
+ void WriteSdc(Clocks& clocks, std::ostream& file);
+
+ private:
+ void WriteClocks(Clocks& clocks, std::ostream& file);
+ void WriteFalsePaths(std::ostream& file);
+ void WriteMaxDelay(std::ostream& file);
+
+ std::vector<FalsePath> false_paths_;
+ std::vector<TimingPath> timing_paths_;
+};
+
+#endif // _SDC_WRITER_H_
diff --git a/sdc-plugin/set_false_path.cc b/sdc-plugin/set_false_path.cc
new file mode 100644
index 0000000..72bb41c
--- /dev/null
+++ b/sdc-plugin/set_false_path.cc
@@ -0,0 +1,90 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2020 The Symbiflow Authors
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "set_false_path.h"
+#include <regex>
+#include "kernel/log.h"
+#include "sdc_writer.h"
+
+USING_YOSYS_NAMESPACE
+
+void SetFalsePath::help() {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" set_false_path [-quiet] [-from <net_name>] [-to <net_name>] \n");
+ log("\n");
+ log("Set false path on the specified net\n");
+ log("\n");
+ log("Print the output to stdout too. This is useful when all Yosys is "
+ "executed.\n");
+ log("\n");
+ log(" -quiet\n");
+ log(" Don't print the result of the execution to stdout.\n");
+ log("\n");
+ log(" -from\n");
+ log(" List of start points or clocks.\n");
+ log("\n");
+ log(" -to\n");
+ log(" List of end points or clocks.\n");
+ log("\n");
+}
+
+void SetFalsePath::execute(std::vector<std::string> args,
+ RTLIL::Design* design) {
+ RTLIL::Module* top_module = design->top_module();
+ if (top_module == nullptr) {
+ log_cmd_error("No top module detected\n");
+ }
+
+ size_t argidx;
+ bool is_quiet = false;
+ std::string from_pin;
+ std::string to_pin;
+
+ // Parse command arguments
+ for (argidx = 1; argidx < args.size(); argidx++) {
+ std::string arg = args[argidx];
+ if (arg == "-quiet") {
+ is_quiet = true;
+ continue;
+ }
+
+ if (arg == "-from" and argidx + 1 < args.size()) {
+ from_pin = args[++argidx];
+ log("From: %s\n", from_pin.c_str());
+ continue;
+ }
+
+ if (arg == "-to" and argidx + 1 < args.size()) {
+ to_pin = args[++argidx];
+ log("To: %s\n", to_pin.c_str());
+ continue;
+ }
+
+ if (arg.size() > 0 and arg[0] == '-') {
+ log_cmd_error("Unknown option %s.\n", arg.c_str());
+ }
+
+ break;
+ }
+ if (!is_quiet) {
+ std::string msg = (from_pin.empty()) ? "" : "-from " + from_pin;
+ msg += (to_pin.empty()) ? "" : " -to " + to_pin;
+ log("Adding false path %s\n", msg.c_str());
+ }
+ sdc_writer_.AddFalsePath(FalsePath{.from_pin = from_pin, .to_pin = to_pin});
+}
diff --git a/sdc-plugin/set_false_path.h b/sdc-plugin/set_false_path.h
new file mode 100644
index 0000000..47bf08a
--- /dev/null
+++ b/sdc-plugin/set_false_path.h
@@ -0,0 +1,39 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2020 The Symbiflow Authors
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef _SET_FALSE_PATH_H_
+#define _SET_FALSE_PATH_H_
+
+#include "kernel/register.h"
+#include "kernel/rtlil.h"
+#include "sdc_writer.h"
+
+USING_YOSYS_NAMESPACE
+
+struct SetFalsePath : public Pass {
+ SetFalsePath(SdcWriter& sdc_writer)
+ : Pass("set_false_path", "Set false path on net"),
+ sdc_writer_(sdc_writer) {}
+
+ void help() override;
+
+ void execute(std::vector<std::string> args, RTLIL::Design* design) override;
+
+ SdcWriter& sdc_writer_;
+};
+
+#endif //_SET_FALSE_PATH_H_
diff --git a/sdc-plugin/set_max_delay.cc b/sdc-plugin/set_max_delay.cc
new file mode 100644
index 0000000..055e342
--- /dev/null
+++ b/sdc-plugin/set_max_delay.cc
@@ -0,0 +1,92 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2020 The Symbiflow Authors
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include "set_max_delay.h"
+#include "kernel/log.h"
+#include "sdc_writer.h"
+
+USING_YOSYS_NAMESPACE
+
+void SetMaxDelay::help() {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" set_max_delay [-quiet] [-from <arg>] [-to <arg>] \n");
+ log("\n");
+ log("Specify maximum delay for timing paths\n");
+ log("\n");
+ log("Print the output to stdout too. This is useful when all Yosys is "
+ "executed.\n");
+ log("\n");
+ log(" -quiet\n");
+ log(" Don't print the result of the execution to stdout.\n");
+ log("\n");
+ log(" -from\n");
+ log(" List of start points or clocks.\n");
+ log("\n");
+ log(" -to\n");
+ log(" List of end points or clocks.\n");
+ log("\n");
+}
+
+void SetMaxDelay::execute(std::vector<std::string> args,
+ RTLIL::Design* design) {
+ RTLIL::Module* top_module = design->top_module();
+ if (top_module == nullptr) {
+ log_cmd_error("No top module detected\n");
+ }
+
+ size_t argidx;
+ bool is_quiet = false;
+ std::string from_pin;
+ std::string to_pin;
+ float max_delay(0.0);
+
+ // Parse command arguments
+ for (argidx = 1; argidx < args.size(); argidx++) {
+ std::string arg = args[argidx];
+ if (arg == "-quiet") {
+ is_quiet = true;
+ continue;
+ }
+
+ if (arg == "-from" and argidx + 1 < args.size()) {
+ from_pin = args[++argidx];
+ log("From: %s\n", from_pin.c_str());
+ continue;
+ }
+
+ if (arg == "-to" and argidx + 1 < args.size()) {
+ to_pin = args[++argidx];
+ log("To: %s\n", to_pin.c_str());
+ continue;
+ }
+
+ if (arg.size() > 0 and arg[0] == '-') {
+ log_cmd_error("Unknown option %s.\n", arg.c_str());
+ }
+
+ max_delay = std::stof(args[argidx]);
+ }
+
+ if (!is_quiet) {
+ std::string msg = (from_pin.empty()) ? "" : "-from " + from_pin;
+ msg += (to_pin.empty()) ? "" : " -to " + to_pin;
+ log("Adding max path delay of %f on path %s\n", max_delay, msg.c_str());
+ }
+ sdc_writer_.SetMaxDelay(TimingPath{
+ .from_pin = from_pin, .to_pin = to_pin, .max_delay = max_delay});
+}
diff --git a/sdc-plugin/set_max_delay.h b/sdc-plugin/set_max_delay.h
new file mode 100644
index 0000000..7272839
--- /dev/null
+++ b/sdc-plugin/set_max_delay.h
@@ -0,0 +1,39 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2020 The Symbiflow Authors
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef _SET_MAX_DELAY_H_
+#define _SET_MAX_DELAY_H_
+
+#include "kernel/register.h"
+#include "kernel/rtlil.h"
+#include "sdc_writer.h"
+
+USING_YOSYS_NAMESPACE
+
+struct SetMaxDelay : public Pass {
+ SetMaxDelay(SdcWriter& sdc_writer)
+ : Pass("set_max_delay", "Specify maximum delay for timing paths"),
+ sdc_writer_(sdc_writer) {}
+
+ void help() override;
+
+ void execute(std::vector<std::string> args, RTLIL::Design* design) override;
+
+ SdcWriter& sdc_writer_;
+};
+
+#endif //_SET_MAX_DELAY_H_
diff --git a/sdc-plugin/tests/Makefile b/sdc-plugin/tests/Makefile
index d19f19d..718241c 100644
--- a/sdc-plugin/tests/Makefile
+++ b/sdc-plugin/tests/Makefile
@@ -1,4 +1,16 @@
-TESTS = counter counter2 pll pll_div pll_fbout_phase pll_approx_equal
+# counter, counter2, pll - test buffer and clock divider propagation
+# set_false_path - test the set_false_path command
+# set_max_delay - test the set_max_delay command
+
+TESTS = counter \
+ counter2 \
+ pll \
+ pll_div \
+ pll_fbout_phase \
+ pll_approx_equal \
+ set_false_path \
+ set_max_delay
+
.PHONY: $(TESTS)
counter_verify = $(call compare,counter,sdc) && $(call compare,counter,txt)
@@ -7,6 +19,8 @@
pll_div_verify = $(call compare,pll_div,sdc)
pll_fbout_phase_verify = $(call compare,pll_fbout_phase,sdc)
pll_approx_equal_verify = $(call compare,pll_approx_equal,sdc)
+set_false_path_verify = $(call compare,set_false_path,sdc)
+set_max_delay_verify = $(call compare,set_max_delay,sdc)
all: $(TESTS)
compare = diff $(1)/$(1).golden.$(2) $(1)/$(1).$(2)
diff --git a/sdc-plugin/tests/set_false_path/set_false_path.golden.sdc b/sdc-plugin/tests/set_false_path/set_false_path.golden.sdc
new file mode 100644
index 0000000..4e75de4
--- /dev/null
+++ b/sdc-plugin/tests/set_false_path/set_false_path.golden.sdc
@@ -0,0 +1,3 @@
+set_false_path -to inter_wire
+set_false_path -from clk
+set_false_path -from clk -to bottom_inst.I
diff --git a/sdc-plugin/tests/set_false_path/set_false_path.tcl b/sdc-plugin/tests/set_false_path/set_false_path.tcl
new file mode 100644
index 0000000..39a51c0
--- /dev/null
+++ b/sdc-plugin/tests/set_false_path/set_false_path.tcl
@@ -0,0 +1,19 @@
+yosys -import
+plugin -i sdc
+#Import the commands from the plugins to the tcl interpreter
+yosys -import
+
+read_verilog set_false_path.v
+# Some of symbiflow expects eblifs with only one module.
+synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
+
+# -to inter_wire net
+set_false_path -to inter_wire
+
+# -from clk net (quiet)
+set_false_path -quiet -from clk
+
+# -from clk to bottom_inst/I
+set_false_path -from clk -to bottom_inst.I
+
+write_sdc set_false_path.sdc
diff --git a/sdc-plugin/tests/set_false_path/set_false_path.v b/sdc-plugin/tests/set_false_path/set_false_path.v
new file mode 100644
index 0000000..d40055b
--- /dev/null
+++ b/sdc-plugin/tests/set_false_path/set_false_path.v
@@ -0,0 +1,75 @@
+module top (
+ (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) input clk,
+ output [3:0] led,
+ inout out_a,
+ output [1:0] out_b,
+ output signal_p,
+ output signal_n
+);
+
+ wire LD6, LD7, LD8, LD9;
+ wire inter_wire, inter_wire_2;
+ localparam BITS = 1;
+ localparam LOG2DELAY = 25;
+
+ reg [BITS+LOG2DELAY-1:0] counter = 0;
+
+ always @(posedge clk) begin
+ counter <= counter + 1;
+ end
+ assign led[1] = inter_wire;
+ assign inter_wire = inter_wire_2;
+ assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
+ OBUFTDS OBUFTDS_2(
+ .I(LD6),
+ .O(signal_p),
+ .OB(signal_n),
+ .T(1'b1)
+ );
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_6(.I(LD6), .O(led[0]));
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_7(.I(LD7), .O(inter_wire_2));
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_OUT(.I(LD7), .O(out_a));
+ bottom bottom_inst(.I(LD8), .O(led[2]), .OB(out_b));
+ bottom_intermediate bottom_intermediate_inst(.I(LD9), .O(led[3]));
+endmodule
+
+module bottom_intermediate (
+ input I,
+ output O
+);
+ wire bottom_intermediate_wire;
+ assign O = bottom_intermediate_wire;
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_8(.I(I), .O(bottom_intermediate_wire));
+endmodule
+
+module bottom (
+ input I,
+ output [1:0] OB,
+ output O
+);
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_9(.I(I), .O(O));
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_10(.I(I), .O(OB[0]));
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_11(.I(I), .O(OB[1]));
+endmodule
+
diff --git a/sdc-plugin/tests/set_max_delay/set_max_delay.golden.sdc b/sdc-plugin/tests/set_max_delay/set_max_delay.golden.sdc
new file mode 100644
index 0000000..02ed95d
--- /dev/null
+++ b/sdc-plugin/tests/set_max_delay/set_max_delay.golden.sdc
@@ -0,0 +1,3 @@
+set_max_delay 1 -to inter_wire
+set_max_delay 2 -from clk
+set_max_delay 3 -from clk -to bottom_inst.I
diff --git a/sdc-plugin/tests/set_max_delay/set_max_delay.tcl b/sdc-plugin/tests/set_max_delay/set_max_delay.tcl
new file mode 100644
index 0000000..8cfde6a
--- /dev/null
+++ b/sdc-plugin/tests/set_max_delay/set_max_delay.tcl
@@ -0,0 +1,19 @@
+yosys -import
+plugin -i sdc
+#Import the commands from the plugins to the tcl interpreter
+yosys -import
+
+read_verilog set_max_delay.v
+# Some of symbiflow expects eblifs with only one module.
+synth_xilinx -vpr -flatten -abc9 -nosrl -noclkbuf -nodsp
+
+# -to inter_wire net
+set_max_delay 1 -to inter_wire
+
+# -from clk net (quiet)
+set_max_delay 2 -quiet -from clk
+
+# -from clk to bottom_inst/I
+set_max_delay 3 -from clk -to bottom_inst.I
+
+write_sdc set_max_delay.sdc
diff --git a/sdc-plugin/tests/set_max_delay/set_max_delay.v b/sdc-plugin/tests/set_max_delay/set_max_delay.v
new file mode 100644
index 0000000..d40055b
--- /dev/null
+++ b/sdc-plugin/tests/set_max_delay/set_max_delay.v
@@ -0,0 +1,75 @@
+module top (
+ (* async_reg = "true", mr_ff = "true", dont_touch = "true" *) input clk,
+ output [3:0] led,
+ inout out_a,
+ output [1:0] out_b,
+ output signal_p,
+ output signal_n
+);
+
+ wire LD6, LD7, LD8, LD9;
+ wire inter_wire, inter_wire_2;
+ localparam BITS = 1;
+ localparam LOG2DELAY = 25;
+
+ reg [BITS+LOG2DELAY-1:0] counter = 0;
+
+ always @(posedge clk) begin
+ counter <= counter + 1;
+ end
+ assign led[1] = inter_wire;
+ assign inter_wire = inter_wire_2;
+ assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
+ OBUFTDS OBUFTDS_2(
+ .I(LD6),
+ .O(signal_p),
+ .OB(signal_n),
+ .T(1'b1)
+ );
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_6(.I(LD6), .O(led[0]));
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_7(.I(LD7), .O(inter_wire_2));
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_OUT(.I(LD7), .O(out_a));
+ bottom bottom_inst(.I(LD8), .O(led[2]), .OB(out_b));
+ bottom_intermediate bottom_intermediate_inst(.I(LD9), .O(led[3]));
+endmodule
+
+module bottom_intermediate (
+ input I,
+ output O
+);
+ wire bottom_intermediate_wire;
+ assign O = bottom_intermediate_wire;
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_8(.I(I), .O(bottom_intermediate_wire));
+endmodule
+
+module bottom (
+ input I,
+ output [1:0] OB,
+ output O
+);
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_9(.I(I), .O(O));
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_10(.I(I), .O(OB[0]));
+ OBUF #(
+ .IOSTANDARD("LVCMOS33"),
+ .SLEW("SLOW")
+ ) OBUF_11(.I(I), .O(OB[1]));
+endmodule
+
