)]}'
{
  "commit": "42cdb06022587d2723a3aae4581fe08e7adaeaee",
  "tree": "3cf5f56f244ff34a379f21adb9266fee82549e15",
  "parents": [
    "d5b617ece0b2b46c09c15c5bddda381f84f6b4ad",
    "a26964a0233c0488479295403021ac23aeb3d02b"
  ],
  "author": {
    "name": "Rafal Kapuscik",
    "email": "54976862+rkapuscik@users.noreply.github.com",
    "time": "Fri Nov 04 09:17:42 2022 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Nov 04 09:17:42 2022 +0100"
  },
  "message": "Merge pull request #392 from antmicro/assign-op-type\n\nsystemverilog: Support op type on assignment",
  "tree_diff": []
}