Set initial state of all k6n10f DSP registers to zero.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
diff --git a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
index 6dac58b..f2e7b05 100644
--- a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
+++ b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
@@ -1472,6 +1472,22 @@
reg r_rnd;
reg [NBITS_ACC-1:0] acc;
+ initial begin
+ r_a <= 'h0;
+ r_b <= 'h0;
+
+ r_acc_fir <= 0;
+ r_unsigned_a <= 0;
+ r_unsigned_b <= 0;
+ r_feedback <= 0;
+ r_shift_d1 <= 0;
+ r_shift_d2 <= 0;
+ r_subtract <= 0;
+ r_load_acc <= 0;
+ r_sat <= 0;
+ r_rnd <= 0;
+ end
+
always @(posedge clock_i or negedge reset_n_i) begin
if (~reset_n_i) begin
@@ -1566,7 +1582,9 @@
wire [NBITS_ACC-1:0] add_o = add_a + add_b;
- // Accumulator
+ // Accumulator
+ initial acc <= 0;
+
always @(posedge clock_i or negedge reset_n_i)
if (~reset_n_i) acc <= 'h0;
else begin
@@ -1603,6 +1621,8 @@
assign z0 = mult_xtnd[NBITS_Z-1:0];
assign z2 = acc_sat[NBITS_Z-1:0];
+ initial z1 <= 0;
+
always @(posedge clock_i or negedge reset_n_i)
if (!reset_n_i)
z1 <= 0;
@@ -1621,6 +1641,8 @@
z1; // if output_select_i == 3'h7
// B input delayed passthrough
+ initial dly_b_o <= 0;
+
always @(posedge clock_i or negedge reset_n_i)
if (!reset_n_i)
dly_b_o <= 0;
diff --git a/ql-qlf-plugin/tests/qlf_k6n10f/sim_dsp_mult_r/sim_dsp_mult_r.v b/ql-qlf-plugin/tests/qlf_k6n10f/sim_dsp_mult_r/sim_dsp_mult_r.v
index 6187e1a..fbc1ba9 100644
--- a/ql-qlf-plugin/tests/qlf_k6n10f/sim_dsp_mult_r/sim_dsp_mult_r.v
+++ b/ql-qlf-plugin/tests/qlf_k6n10f/sim_dsp_mult_r/sim_dsp_mult_r.v
@@ -58,6 +58,7 @@
// Error detection
reg [37:0] r_C;
+ initial r_C <= 0;
always @(posedge clk)
r_C <= C;
