SDC: abc9: Fix test
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
diff --git a/sdc-plugin/tests/abc9/abc9.sdc b/sdc-plugin/tests/abc9/abc9.input.sdc
similarity index 100%
rename from sdc-plugin/tests/abc9/abc9.sdc
rename to sdc-plugin/tests/abc9/abc9.input.sdc
diff --git a/sdc-plugin/tests/abc9/abc9.tcl b/sdc-plugin/tests/abc9/abc9.tcl
index 22766a1..ba71334 100644
--- a/sdc-plugin/tests/abc9/abc9.tcl
+++ b/sdc-plugin/tests/abc9/abc9.tcl
@@ -5,8 +5,8 @@
# ensure abc9.D is unset
scratchpad -assert-unset abc9.D
-read_verilog abc9.v
-read_sdc abc9.sdc
+read_verilog $::env(DESIGN_TOP).v
+read_sdc $::env(DESIGN_TOP).input.sdc
# check that abc9.D was set to half the fastest clock period in the design
scratchpad -assert abc9.D 5000
