)]}'
{
  "commit": "4ad4106e693d0af0166b360b0e0e70d70c44568e",
  "tree": "d6f8c17402e9473306503858b23c9ea0dc507106",
  "parents": [
    "f114817380d98f70431947b4f63b8e720f4725a9"
  ],
  "author": {
    "name": "Mariusz Glebocki",
    "email": "mglebocki@antmicro.com",
    "time": "Thu Apr 27 19:31:34 2023 +0200"
  },
  "committer": {
    "name": "Mariusz Glebocki",
    "email": "mglebocki@antmicro.com",
    "time": "Thu Apr 27 19:31:34 2023 +0200"
  },
  "message": "Use uhdmast_assert in `process_stream_op`.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ee35cd7b7ac57e94928c0b02510d8ffd88d56622",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "4fbd38c2adee5307e698877db55ecac0807266f7",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}