)]}'
{
  "commit": "4b2f1781f2d7571d7b6a4d18ad1a3f638e55b49f",
  "tree": "79d13c170f563af1b18e0a5db265cb192763672d",
  "parents": [
    "74dd5293cd04da9d026057a177394b738627cc8c"
  ],
  "author": {
    "name": "Wojciech Sipak",
    "email": "wsipak@antmicro.com",
    "time": "Mon Jan 23 18:46:48 2023 +0100"
  },
  "committer": {
    "name": "Wojciech Sipak",
    "email": "wsipak@antmicro.com",
    "time": "Wed Jan 25 15:04:18 2023 +0100"
  },
  "message": "handle vpiTypeParameter\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "54a25249ff3387d9de298a0312165b5999777ed4",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "011ae1210022a8bd04517ff70cda777798f4ccfb",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}