diff --git a/Makefile_test.common b/Makefile_test.common
index 61abadb..6497321 100644
--- a/Makefile_test.common
+++ b/Makefile_test.common
@@ -35,11 +35,11 @@
 	@set +e; \
 	$$($(1)_verify); \
 	if [ $$$$? -eq 0 ]; then \
-		printf "Test %-18s \e[32mPASSED\e[0m @ %s\n" $(1) $(CURDIR); \
+		printf "Test %-20s \e[32mPASSED\e[0m @ %s\n" $(1) $(CURDIR); \
 		touch $$<; \
 		true; \
 	else \
-		printf "Test %-18s \e[31;1mFAILED\e[0m @ %s\n" $(1) $(CURDIR); \
+		printf "Test %-20s \e[31;1mFAILED\e[0m @ %s\n" $(1) $(CURDIR); \
 		false; \
 	fi
 
@@ -54,15 +54,15 @@
 	rm -f run-$(1).tcl; \
 	if [ ! -z "$$($(1)_negative)" ] && [ $$($(1)_negative) -eq 1 ]; then \
 		if [ $$$$RETVAL -ne 0 ]; then \
-			printf "Negative test %-18s \e[32mPASSED\e[0m @ %s\n" $(1) $(CURDIR); \
+			printf "Negative test %-20s \e[32mPASSED\e[0m @ %s\n" $(1) $(CURDIR); \
 			true; \
 		else \
-			printf "Negative test %-18s \e[31;1mFAILED\e[0m @ %s\n" $(1) $(CURDIR); \
+			printf "Negative test %-20s \e[31;1mFAILED\e[0m @ %s\n" $(1) $(CURDIR); \
 			false; \
 		fi \
 	else \
 		if [ $$$$RETVAL -ne 0 ]; then \
-			echo "Unexpected runtime error"; \
+		    printf "Test %-20s \e[31;1mFAILED\e[0m @ %s\n" $(1) $(CURDIR); \
 			false; \
 		fi \
 	fi
diff --git a/dsp_ff-plugin/nexus-dsp_rules.txt b/dsp_ff-plugin/nexus-dsp_rules.txt
index 934eea5..7d35b84 100644
--- a/dsp_ff-plugin/nexus-dsp_rules.txt
+++ b/dsp_ff-plugin/nexus-dsp_rules.txt
@@ -162,7 +162,7 @@
   q   Q
 
   match GSR
-  set RESETMODE=SYNC
+  set RESETMODE=ASYNC
 endff
 
 ff FD1P3IX
@@ -173,6 +173,6 @@
   q   Q
 
   match GSR
-  set RESETMODE=ASYNC
+  set RESETMODE=SYNC
 endff
 
diff --git a/dsp_ff-plugin/tests/Makefile b/dsp_ff-plugin/tests/Makefile
index 76ffd64..d559175 100644
--- a/dsp_ff-plugin/tests/Makefile
+++ b/dsp_ff-plugin/tests/Makefile
@@ -7,8 +7,16 @@
 # SPDX-License-Identifier:ISC
 
 TESTS = \
-    nexus_mult
+    nexus_mult \
+    nexus_fftypes \
+    nexus_conn_conflict \
+    nexus_conn_share \
+    nexus_param_conflict
 
 include $(shell pwd)/../../Makefile_test.common
 
 nexus_mult_verify = true
+nexus_fftypes_verify = true
+nexus_conn_conflict_verify = true
+nexus_conn_share_verify = true
+nexus_param_conflict_verify = true
diff --git a/dsp_ff-plugin/tests/nexus_conn_conflict/nexus_conn_conflict.tcl b/dsp_ff-plugin/tests/nexus_conn_conflict/nexus_conn_conflict.tcl
new file mode 100644
index 0000000..c4cee75
--- /dev/null
+++ b/dsp_ff-plugin/tests/nexus_conn_conflict/nexus_conn_conflict.tcl
@@ -0,0 +1,48 @@
+yosys -import
+if { [info procs dsp_ff] == {} } { plugin -i dsp-ff }
+yosys -import  ;# ingest plugin commands
+
+read_verilog $::env(DESIGN_TOP).v
+design -save read
+
+set TOP "conflict_dsp_clk"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+design -load postopt
+yosys cd ${TOP}
+stat
+select -assert-count 1 t:MULT9X9
+select -assert-count 9 t:FD1P3IX
+
+set TOP "conflict_ff_clk"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+debug dsp_ff -rules ../../nexus-dsp_rules.txt
+stat
+select -assert-count 1 t:MULT9X9
+select -assert-count 18 t:FD1P3IX
+
+set TOP "conflict_ff_rst"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+debug dsp_ff -rules ../../nexus-dsp_rules.txt
+stat
+select -assert-count 1 t:MULT9X9
+select -assert-count 18 t:FD1P3DX
+
+set TOP "conflict_ff_ena"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+debug dsp_ff -rules ../../nexus-dsp_rules.txt
+stat
+select -assert-count 1 t:MULT9X9
+select -assert-count 18 t:FD1P3IX
diff --git a/dsp_ff-plugin/tests/nexus_conn_conflict/nexus_conn_conflict.v b/dsp_ff-plugin/tests/nexus_conn_conflict/nexus_conn_conflict.v
new file mode 100644
index 0000000..2eb8634
--- /dev/null
+++ b/dsp_ff-plugin/tests/nexus_conn_conflict/nexus_conn_conflict.v
@@ -0,0 +1,120 @@
+module conflict_dsp_clk (
+    input  wire        CLK_A,
+    input  wire        CLK_B,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output wire [17:0] Z
+);
+
+    reg [8:0] ra;
+    always @(posedge CLK_A)
+        ra <= A;
+
+    reg [8:0] rb;
+    always @(posedge CLK_B)
+        rb <= B;
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A (ra),
+        .B (rb),
+        .Z (Z)
+    );
+
+endmodule
+
+module conflict_ff_clk (
+    input  wire        CLK1,
+    input  wire        CLK2,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output wire [17:0] Z
+);
+
+    reg [17:0] z;
+
+    always @(posedge CLK1)
+        Z[17:9] <= z[17:9];
+    always @(posedge CLK2)
+        Z[ 8:0] <= z[ 8:0];
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A (A),
+        .B (B),
+        .Z (z)
+    );
+
+endmodule
+
+module conflict_ff_rst (
+    input  wire        CLK,
+    input  wire        RST1,
+    input  wire        RST2,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output wire [17:0] Z
+);
+
+    reg [17:0] z;
+
+    always @(posedge CLK or posedge RST1)
+        if (RST1)
+            Z[17:9] <= 0;
+        else
+            Z[17:9] <= z[17:9];
+    always @(posedge CLK or posedge RST2)
+        if (RST2)
+            Z[ 8:0] <= 0;
+        else
+            Z[ 8:0] <= z[ 8:0];
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A (A),
+        .B (B),
+        .Z (z)
+    );
+
+endmodule
+
+module conflict_ff_ena (
+    input  wire        CLK,
+    input  wire        ENA1,
+    input  wire        ENA2,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output wire [17:0] Z
+);
+
+    reg [17:0] z;
+
+    always @(posedge CLK)
+        if (ENA1)
+            Z[17:9] <= z[17:9];
+    always @(posedge CLK)
+        if (ENA2)
+            Z[ 8:0] <= z[ 8:0];
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A (A),
+        .B (B),
+        .Z (z)
+    );
+
+endmodule
+
+
diff --git a/dsp_ff-plugin/tests/nexus_conn_share/nexus_conn_share.tcl b/dsp_ff-plugin/tests/nexus_conn_share/nexus_conn_share.tcl
new file mode 100644
index 0000000..2f13e67
--- /dev/null
+++ b/dsp_ff-plugin/tests/nexus_conn_share/nexus_conn_share.tcl
@@ -0,0 +1,48 @@
+yosys -import
+if { [info procs dsp_ff] == {} } { plugin -i dsp-ff }
+yosys -import  ;# ingest plugin commands
+
+read_verilog $::env(DESIGN_TOP).v
+design -save read
+
+set TOP "conflict_out_fanout"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+debug dsp_ff -rules ../../nexus-dsp_rules.txt
+stat
+select -assert-count 1 t:MULT9X9
+select -assert-count 18 t:FD1P3IX
+
+set TOP "conflict_out_fanout_to_top"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+debug dsp_ff -rules ../../nexus-dsp_rules.txt
+stat
+select -assert-count 1 t:MULT9X9
+select -assert-count 18 t:FD1P3IX
+
+set TOP "conflict_inp_fanout"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+debug dsp_ff -rules ../../nexus-dsp_rules.txt
+stat
+select -assert-count 1 t:MULT9X9
+select -assert-count 9 t:FD1P3IX
+
+set TOP "conflict_inp_fanout_to_top"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+debug dsp_ff -rules ../../nexus-dsp_rules.txt
+stat
+select -assert-count 1 t:MULT9X9
+select -assert-count 9 t:FD1P3IX
+
+
diff --git a/dsp_ff-plugin/tests/nexus_conn_share/nexus_conn_share.v b/dsp_ff-plugin/tests/nexus_conn_share/nexus_conn_share.v
new file mode 100644
index 0000000..856cda8
--- /dev/null
+++ b/dsp_ff-plugin/tests/nexus_conn_share/nexus_conn_share.v
@@ -0,0 +1,104 @@
+module conflict_out_fanout (
+    input  wire        CLK,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output reg  [17:0] Z,
+    output wire [ 8:0] X,
+);
+
+    wire [17:0] z;
+    always @(posedge CLK)
+        Z <= z;
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A (A),
+        .B (B),
+        .Z (z)
+    );
+
+    assign X = ~z[8:0];
+
+endmodule
+
+module conflict_out_fanout_to_top (
+    input  wire        CLK,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output reg  [17:0] Z,
+    output wire [ 8:0] X,
+);
+
+    wire [17:0] z;
+    always @(posedge CLK)
+        Z <= z;
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A (A),
+        .B (B),
+        .Z (z)
+    );
+
+    assign X = z[8:0];
+
+endmodule
+
+module conflict_inp_fanout (
+    input  wire        CLK,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output reg  [17:0] Z,
+    output wire [ 3:0] X,
+);
+
+    wire [8:0] ra;
+    always @(posedge CLK)
+        ra <= A;
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A (ra),
+        .B (B),
+        .Z (Z)
+    );
+
+    assign X = ~ra[3:0];
+
+endmodule
+
+module conflict_inp_fanout_to_top (
+    input  wire        CLK,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output reg  [17:0] Z,
+    output wire [ 3:0] X,
+);
+
+    wire [8:0] ra;
+    always @(posedge CLK)
+        ra <= A;
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A (ra),
+        .B (B),
+        .Z (Z)
+    );
+
+    assign X = ra[3:0];
+
+endmodule
+
diff --git a/dsp_ff-plugin/tests/nexus_fftypes/nexus_fftypes.tcl b/dsp_ff-plugin/tests/nexus_fftypes/nexus_fftypes.tcl
new file mode 100644
index 0000000..fa006c8
--- /dev/null
+++ b/dsp_ff-plugin/tests/nexus_fftypes/nexus_fftypes.tcl
@@ -0,0 +1,71 @@
+yosys -import
+if { [info procs dsp_ff] == {} } { plugin -i dsp-ff }
+yosys -import  ;# ingest plugin commands
+
+read_verilog $::env(DESIGN_TOP).v
+design -save read
+
+set TOP "mult_ena"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+design -load postopt
+yosys cd ${TOP}
+stat
+select -assert-count 1 t:MULT9X9
+select -assert-count 0 t:FD1P3IX
+select -assert-count 0 t:FD1P3DX
+
+set TOP "mult_arst"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+design -load postopt
+yosys cd ${TOP}
+stat
+select -assert-count 1 t:MULT9X9
+select -assert-count 0 t:FD1P3IX
+select -assert-count 0 t:FD1P3DX
+
+set TOP "mult_arst_ena"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+design -load postopt
+yosys cd ${TOP}
+stat
+select -assert-count 1 t:MULT9X9
+select -assert-count 0 t:FD1P3IX
+select -assert-count 0 t:FD1P3DX
+
+set TOP "mult_srst"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+design -load postopt
+yosys cd ${TOP}
+stat
+select -assert-count 1 t:MULT9X9
+select -assert-count 0 t:FD1P3IX
+select -assert-count 0 t:FD1P3DX
+
+set TOP "mult_srst_ena"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+design -load postopt
+yosys cd ${TOP}
+stat
+select -assert-count 1 t:MULT9X9
+select -assert-count 0 t:FD1P3IX
+select -assert-count 0 t:FD1P3DX
diff --git a/dsp_ff-plugin/tests/nexus_fftypes/nexus_fftypes.v b/dsp_ff-plugin/tests/nexus_fftypes/nexus_fftypes.v
new file mode 100644
index 0000000..e4f22fe
--- /dev/null
+++ b/dsp_ff-plugin/tests/nexus_fftypes/nexus_fftypes.v
@@ -0,0 +1,126 @@
+module mult_ena (
+    input  wire        CLK,
+    input  wire        ENA,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output wire [17:0] Z
+);
+
+    reg [8:0] ra;
+    always @(posedge CLK)
+        if (ENA) ra <= A;
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A (ra),
+        .B (B),
+        .Z (Z)
+    );
+
+endmodule
+
+module mult_arst (
+    input  wire        CLK,
+    input  wire        RST,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output wire [17:0] Z
+);
+
+    reg [8:0] ra;
+    always @(posedge CLK or posedge RST)
+        if (RST) ra <= 0;
+        else     ra <= A;
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A (ra),
+        .B (B),
+        .Z (Z)
+    );
+
+endmodule
+
+module mult_arst_ena (
+    input  wire        CLK,
+    input  wire        RST,
+    input  wire        ENA,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output wire [17:0] Z
+);
+
+    reg [8:0] ra;
+    always @(posedge CLK or posedge RST)
+        if (RST)      ra <= 0;
+        else if (ENA) ra <= A;
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A (ra),
+        .B (B),
+        .Z (Z)
+    );
+
+endmodule
+
+module mult_srst (
+    input  wire        CLK,
+    input  wire        RST,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output wire [17:0] Z
+);
+
+    reg [8:0] ra;
+    always @(posedge CLK)
+        if (RST) ra <= 0;
+        else     ra <= A;
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A (ra),
+        .B (B),
+        .Z (Z)
+    );
+
+endmodule
+
+module mult_srst_ena (
+    input  wire        CLK,
+    input  wire        RST,
+    input  wire        ENA,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output wire [17:0] Z
+);
+
+    reg [8:0] ra;
+    always @(posedge CLK)
+        if (RST)      ra <= 0;
+        else if (ENA) ra <= A;
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A (ra),
+        .B (B),
+        .Z (Z)
+    );
+
+endmodule
+
diff --git a/dsp_ff-plugin/tests/nexus_mult/nexus_mult.tcl b/dsp_ff-plugin/tests/nexus_mult/nexus_mult.tcl
index 437fe9e..d82ffa8 100644
--- a/dsp_ff-plugin/tests/nexus_mult/nexus_mult.tcl
+++ b/dsp_ff-plugin/tests/nexus_mult/nexus_mult.tcl
@@ -14,8 +14,8 @@
 design -load postopt
 yosys cd ${TOP}
 stat
-select -assert-count MULT9X9 1
-select -assert-count FD1P3IX 0
+select -assert-count 1 t:MULT9X9
+select -assert-count 0 t:FD1P3IX
 
 set TOP "mult_oreg"
 design -load read
@@ -26,8 +26,8 @@
 design -load postopt
 yosys cd ${TOP}
 stat
-select -assert-count MULT9X9 1
-select -assert-count FD1P3IX 0
+select -assert-count 1 t:MULT9X9
+select -assert-count 0 t:FD1P3IX
 
 set TOP "mult_all"
 design -load read
@@ -38,6 +38,6 @@
 design -load postopt
 yosys cd ${TOP}
 stat
-select -assert-count MULT9X9 1
-select -assert-count FD1P3IX 0
+select -assert-count 1 t:MULT9X9
+select -assert-count 0 t:FD1P3IX
 
diff --git a/dsp_ff-plugin/tests/nexus_param_conflict/nexus_param_conflict.tcl b/dsp_ff-plugin/tests/nexus_param_conflict/nexus_param_conflict.tcl
new file mode 100644
index 0000000..abd9d3c
--- /dev/null
+++ b/dsp_ff-plugin/tests/nexus_param_conflict/nexus_param_conflict.tcl
@@ -0,0 +1,40 @@
+yosys -import
+if { [info procs dsp_ff] == {} } { plugin -i dsp-ff }
+yosys -import  ;# ingest plugin commands
+
+read_verilog $::env(DESIGN_TOP).v
+design -save read
+
+set TOP "conflict_dsp_ctrl_param"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+debug dsp_ff -rules ../../nexus-dsp_rules.txt
+stat
+select -assert-count 1 t:MULT9X9
+select -assert-count 18 t:FD1P3IX
+
+set TOP "conflict_dsp_common_param"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+equiv_opt -assert -async2sync -map +/nexus/cells_sim.v debug dsp_ff -rules ../../nexus-dsp_rules.txt
+design -load postopt
+yosys cd ${TOP}
+stat
+select -assert-count 1 t:MULT9X9
+select -assert-count 9 t:FD1P3IX t:DS1P3DX %u
+
+set TOP "conflict_ff_param"
+design -load read
+hierarchy -top ${TOP}
+synth_nexus -flatten
+techmap -map +/nexus/cells_sim.v t:VLO t:VHI %u ;# Unmap VHI and VLO
+debug dsp_ff -rules ../../nexus-dsp_rules.txt
+stat
+select -assert-count 1 t:MULT9X9
+select -assert-count 4 t:FD1P3IX
+select -assert-count 5 t:FD1P3DX
+
diff --git a/dsp_ff-plugin/tests/nexus_param_conflict/nexus_param_conflict.v b/dsp_ff-plugin/tests/nexus_param_conflict/nexus_param_conflict.v
new file mode 100644
index 0000000..d03d611
--- /dev/null
+++ b/dsp_ff-plugin/tests/nexus_param_conflict/nexus_param_conflict.v
@@ -0,0 +1,82 @@
+module conflict_dsp_ctrl_param (
+    input  wire        CLK,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output reg  [17:0] Z,
+);
+
+    wire [17:0] z;
+    always @(posedge CLK)
+        Z <= z;
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("REGISTER")
+    ) mult (
+        .A (A),
+        .B (B),
+        .Z (z)
+    );
+
+endmodule
+
+module conflict_dsp_common_param (
+    input  wire        CLK,
+    input  wire        RST,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output wire [17:0] Z,
+);
+
+    wire [8:0] ra;
+    always @(posedge CLK or posedge RST)
+        if (RST) ra <= 0;
+        else     ra <= A;
+
+    wire [8:0] rb;
+    always @(posedge CLK)
+        if (RST) rb <= 0;
+        else     rb <= B;
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A (ra),
+        .B (rb),
+        .Z (Z)
+    );
+
+endmodule
+
+module conflict_ff_param (
+    input  wire        CLK,
+    input  wire        RST,
+    input  wire [ 8:0] A,
+    input  wire [ 8:0] B,
+    output wire [17:0] Z,
+);
+
+    wire [8:0] ra;
+    always @(posedge CLK or posedge RST)
+        if (RST) ra[8:4] <= 0;
+        else     ra[8:4] <= A[8:4];
+
+    always @(posedge CLK)
+        if (RST) ra[3:0] <= 0;
+        else     ra[3:0] <= A[3:0];
+
+    MULT9X9 # (
+        .REGINPUTA("BYPASS"),
+        .REGINPUTB("BYPASS"),
+        .REGOUTPUT("BYPASS")
+    ) mult (
+        .A (ra),
+        .B (B),
+        .Z (Z)
+    );
+
+endmodule
+