)]}'
{
  "commit": "4d987efc3d970f1b8da7b80bf63c3486b9e3e2be",
  "tree": "dd58b7dfdf8be63b4e3803ae1b8ba4b3cd011170",
  "parents": [
    "0f72816c9904126f3f29838df66e082dd80bb588"
  ],
  "author": {
    "name": "Rafal Kapuscik",
    "email": "rkapuscik@antmicro.com",
    "time": "Tue May 31 13:48:15 2022 +0200"
  },
  "committer": {
    "name": "Rafal Kapuscik",
    "email": "rkapuscik@antmicro.com",
    "time": "Tue May 31 14:04:44 2022 +0200"
  },
  "message": "Handle missing typespecs\n\nSigned-off-by: Rafal Kapuscik \u003crkapuscik@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a112da14daadbd3852b2c70cf124a51b8ccd7abe",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "1d2383e8ba2313b89d0a0e37d1a8d46ec8e0d224",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}