)]}'
{
  "commit": "4ea2ebf5e47acaabeb41a26e089d740c80e9d889",
  "tree": "4722534341b105f8cd196109e849dba21fca038a",
  "parents": [
    "e0a923cc0bf6b2149994857ba47dc71c5791f227"
  ],
  "author": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Tue Mar 14 09:30:48 2023 +0100"
  },
  "committer": {
    "name": "Kamil Rakoczy",
    "email": "krakoczy@antmicro.com",
    "time": "Mon Mar 27 13:10:38 2023 +0200"
  },
  "message": "systemverilog-plugin: use custom simplification step before yosys\n\nSigned-off-by: Kamil Rakoczy \u003ckrakoczy@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2dc7f0c724b25d90aeac69592db1926d7b3d85ad",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "d069d53275f3d297019dfdc9ba11e17c79e4ae77",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}