)]}'
{
  "commit": "56efb7460aef981788b35bbba6be108632337eec",
  "tree": "4ed682f4de35e4437320483a239bf0e707c8f7dd",
  "parents": [
    "e5a04f5f8499ef2252d8e8d58c2e75fce717cde5"
  ],
  "author": {
    "name": "Tomasz Michalak",
    "email": "tmichalak@antmicro.com",
    "time": "Thu Sep 10 17:28:21 2020 +0200"
  },
  "committer": {
    "name": "Tomasz Michalak",
    "email": "tmichalak@antmicro.com",
    "time": "Tue Sep 15 16:35:26 2020 +0200"
  },
  "message": "SDC: Add duty cycle and input clock delay to output clock\n\nSigned-off-by: Tomasz Michalak \u003ctmichalak@antmicro.com\u003e\n",
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