tree 4ed682f4de35e4437320483a239bf0e707c8f7dd
parent e5a04f5f8499ef2252d8e8d58c2e75fce717cde5
author Tomasz Michalak <tmichalak@antmicro.com> 1599751701 +0200
committer Tomasz Michalak <tmichalak@antmicro.com> 1600180526 +0200

SDC: Add duty cycle and input clock delay to output clock

Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>