)]}'
{
  "commit": "574995bb0810611375250d3ad91e45615b878d89",
  "tree": "a5d370adf65778eb10c533c8f9f6d8e5765e1f70",
  "parents": [
    "80c05c505da9982a597aa4a4e5c64b92306e3656",
    "621198f722001bf322b9762bfaf8d5669929c093"
  ],
  "author": {
    "name": "Tomasz Michalak",
    "email": "tmichalak@antmicro.com",
    "time": "Thu Oct 01 08:13:03 2020 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Oct 01 08:13:03 2020 +0200"
  },
  "message": "Merge pull request #37 from antmicro/clock_divider_input_phase_fix\n\nSDC: Handle input clock phase shift on clock generators",
  "tree_diff": []
}