tree a5d370adf65778eb10c533c8f9f6d8e5765e1f70
parent 80c05c505da9982a597aa4a4e5c64b92306e3656
parent 621198f722001bf322b9762bfaf8d5669929c093
author Tomasz Michalak <tmichalak@antmicro.com> 1601532783 +0200
committer GitHub <noreply@github.com> 1601532783 +0200
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Merge pull request #37 from antmicro/clock_divider_input_phase_fix

SDC: Handle input clock phase shift on clock generators