)]}'
{
  "commit": "5a7f9874370871b5ecc8462c9cd81ce0a10a16ae",
  "tree": "d69f6b268acefe191434f1b11d79463bee2ca906",
  "parents": [
    "45781feffd33b87b6c111728eb0456749a218888"
  ],
  "author": {
    "name": "Robert Szczepanski",
    "email": "rszczepanski@antmicro.com",
    "time": "Wed Dec 07 16:12:07 2022 +0100"
  },
  "committer": {
    "name": "Robert Szczepanski",
    "email": "rszczepanski@antmicro.com",
    "time": "Fri Jan 13 15:29:47 2023 +0100"
  },
  "message": "systemverilog: Fix memory inference\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0a1b626a1cf16af2d1054150cb985170bd8b9c5b",
      "old_mode": 33188,
      "old_path": "systemverilog-plugin/UhdmAst.cc",
      "new_id": "94a1c24a3b08c0118722c888a9056c73af46f33c",
      "new_mode": 33188,
      "new_path": "systemverilog-plugin/UhdmAst.cc"
    }
  ]
}