SDC: Check if period of CLKIN1_PERIOD is equal to input clock
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
diff --git a/sdc-plugin/buffers.cc b/sdc-plugin/buffers.cc
index 5b42129..ab99888 100644
--- a/sdc-plugin/buffers.cc
+++ b/sdc-plugin/buffers.cc
@@ -29,6 +29,13 @@
assert(RTLIL::unescape_id(cell->type) == "PLLE2_ADV");
FetchParams(cell);
+ if (clkin1_period != input_clock_period) {
+ log_cmd_error(
+ "CLKIN1_PERIOD doesn't match the virtual clock constraint "
+ "propagated to the CLKIN1 input of the clock divider cell: "
+ "%s.\nInput clock period: %f, CLKIN1_PERIOD: %f\n",
+ RTLIL::id2cstr(cell->name), input_clock_period, clkin1_period);
+ }
CalculateOutputClockPeriods();
CalculateOutputClockWaveforms(input_clock_period, input_clock_shift);
}
