Aggregated all QL_DSP2 parameters into a single one named MODE_BITS

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

ql-qlf-plugin/ql-dsp-simd.cc

diff --git a/ql-qlf-plugin/ql-dsp-simd.cc b/ql-qlf-plugin/ql-dsp-simd.cc
index ba40c07..edf432a 100644
--- a/ql-qlf-plugin/ql-dsp-simd.cc
+++ b/ql-qlf-plugin/ql-dsp-simd.cc
@@ -87,7 +87,7 @@
     };
 
     // DSP parameters
-    const std::vector<std::string> m_DspParams = {"COEFF_0", "COEFF_1", "COEFF_2", "COEFF_3"};
+    const std::vector<std::string> m_DspParams = {"COEFF_3", "COEFF_2", "COEFF_1", "COEFF_0"};
 
     // Source DSP cell type (SISD)
     const std::string m_SisdDspType = "dsp_t1_10x9x32";
@@ -206,16 +206,18 @@
                         simd->setPort(dport, sigspec);
                     }
 
-                    // Set parameters
+                    // Concatenate FIR coefficient parameters into the single
+                    // MODE_BITS parameter
+                    std::vector<RTLIL::State> mode_bits;
                     for (const auto &it : m_DspParams) {
                         auto val_a = dsp_a->getParam(RTLIL::escape_id(it));
                         auto val_b = dsp_b->getParam(RTLIL::escape_id(it));
 
-                        std::vector<RTLIL::State> bits;
-                        bits.insert(bits.end(), val_a.begin(), val_a.end());
-                        bits.insert(bits.end(), val_b.begin(), val_b.end());
-                        simd->setParam(RTLIL::escape_id(it), RTLIL::Const(bits));
+                        mode_bits.insert(mode_bits.end(), val_a.begin(), val_a.end());
+                        mode_bits.insert(mode_bits.end(), val_b.begin(), val_b.end());
                     }
+                    simd->setParam(RTLIL::escape_id("MODE_BITS"), RTLIL::Const(mode_bits));
+                    log_assert(mode_bits.size() == 80);
 
                     // Enable the fractured mode by connecting the control
                     // port.

ql-qlf-plugin/qlf_k6n10f/cells_sim.v

diff --git a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
index dff4af3..c669166 100644
--- a/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
+++ b/ql-qlf-plugin/qlf_k6n10f/cells_sim.v
@@ -1291,10 +1291,12 @@
     input         register_inputs
 );
 
-    parameter [19:0] COEFF_0 = 20'd0;
-    parameter [19:0] COEFF_1 = 20'd0;
-    parameter [19:0] COEFF_2 = 20'd0;
-    parameter [19:0] COEFF_3 = 20'd0;
+    parameter [79:0] MODE_BITS = 80'd0;
+
+    localparam [19:0] COEFF_0 = MODE_BITS[19:0];
+    localparam [19:0] COEFF_1 = MODE_BITS[39:20];
+    localparam [19:0] COEFF_2 = MODE_BITS[59:40];
+    localparam [19:0] COEFF_3 = MODE_BITS[79:60];
 
       localparam NBITS_ACC = 64;
       localparam NBITS_A = 20;
@@ -1689,10 +1691,7 @@
     parameter [19:0] COEFF_3 = 20'd0;
 
    QL_DSP2 #(
-        .COEFF_0(COEFF_0),
-        .COEFF_1(COEFF_1),
-        .COEFF_2(COEFF_2),
-        .COEFF_3(COEFF_3)
+    .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
    ) dsp (
     .a(a_i),
     .b(b_i),
@@ -1753,10 +1752,10 @@
     wire [8:0] dly_b_rem;
 
     QL_DSP2 #(
-        .COEFF_0({10'd0, COEFF_0}),
-        .COEFF_1({10'd0, COEFF_1}),
-        .COEFF_2({10'd0, COEFF_2}),
-        .COEFF_3({10'd0, COEFF_3})
+    .MODE_BITS({10'd0, COEFF_3,
+                10'd0, COEFF_2,
+                10'd0, COEFF_1,
+                10'd0, COEFF_0})
    ) dsp (
     .a({10'd0, a_i}),
     .b({9'd0, b_i}),

ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v

diff --git a/ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v b/ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v
index 6967a44..1c56eed 100644
--- a/ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v
+++ b/ql-qlf-plugin/qlf_k6n10f/dsp_final_map.v
@@ -43,10 +43,7 @@
     parameter [19:0] COEFF_3 = 20'd0;
 
     QL_DSP2 # (
-        .COEFF_0            (COEFF_0),
-        .COEFF_1            (COEFF_1),
-        .COEFF_2            (COEFF_2),
-        .COEFF_3            (COEFF_3)
+        .MODE_BITS          ({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
     ) _TECHMAP_REPLACE_ (
         .a                  (a_i),
         .b                  (b_i),
@@ -94,11 +91,7 @@
     input  [5:0]  shift_right_i,
     input         round_i,
     input         subtract_i,
-    input         register_inputs_i,
-    input  [ 9:0] coeff_0_i,
-    input  [ 9:0] coeff_1_i,
-    input  [ 9:0] coeff_2_i,
-    input  [ 9:0] coeff_3_i
+    input         register_inputs_i
 );
 
     parameter [9:0] COEFF_0 = 10'd0;
@@ -110,10 +103,10 @@
     wire [17:0] dly_b;
 
     QL_DSP2 # (
-        .COEFF_0            ({10'd0, COEFF_0}),
-        .COEFF_1            ({10'd0, COEFF_1}),
-        .COEFF_2            ({10'd0, COEFF_2}),
-        .COEFF_3            ({10'd0, COEFF_3})
+        .MODE_BITS          ({10'd0, COEFF_3,
+                              10'd0, COEFF_2,
+                              10'd0, COEFF_1,
+                              10'd0, COEFF_0})
     ) _TECHMAP_REPLACE_ (
         .a                  ({10'd0, a_i}),
         .b                  ({ 9'd0, b_i}),